/dts-v1/;

/ {
	compatible = "libretech,roc-rk3399-pc\0rockchip,rk3399";
	interrupt-parent = <0x01>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	model = "Libre Computer ROC-RK3399-PC";

	aliases {
		ethernet0 = "/ethernet@fe300000";
		i2c0 = "/i2c@ff3c0000";
		i2c1 = "/i2c@ff110000";
		i2c2 = "/i2c@ff120000";
		i2c3 = "/i2c@ff130000";
		i2c4 = "/i2c@ff3d0000";
		i2c5 = "/i2c@ff140000";
		i2c6 = "/i2c@ff150000";
		i2c7 = "/i2c@ff160000";
		i2c8 = "/i2c@ff3e0000";
		serial0 = "/serial@ff180000";
		serial1 = "/serial@ff190000";
		serial2 = "/serial@ff1a0000";
		serial3 = "/serial@ff1b0000";
		serial4 = "/serial@ff370000";
		mmc0 = "/mmc@fe330000";
		mmc1 = "/mmc@fe320000";
		pci0 = "/pcie@f8000000";
		spi1 = "/spi@ff1d0000";
	};

	cpus {
		#address-cells = <0x02>;
		#size-cells = <0x00>;

		cpu-map {

			cluster0 {

				core0 {
					cpu = <0x02>;
				};

				core1 {
					cpu = <0x03>;
				};

				core2 {
					cpu = <0x04>;
				};

				core3 {
					cpu = <0x05>;
				};
			};

			cluster1 {

				core0 {
					cpu = <0x06>;
				};

				core1 {
					cpu = <0x07>;
				};
			};
		};

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x00 0x00>;
			enable-method = "psci";
			next-level-cache = <0x08>;
			capacity-dmips-mhz = <0x1e5>;
			clocks = <0x09 0x08>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x64>;
			cpu-idle-states = <0x0a 0x0b>;
			operating-points-v2 = <0x0c>;
			cpu-supply = <0x0d>;
			phandle = <0x02>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x00 0x01>;
			enable-method = "psci";
			next-level-cache = <0x08>;
			capacity-dmips-mhz = <0x1e5>;
			clocks = <0x09 0x08>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x64>;
			cpu-idle-states = <0x0a 0x0b>;
			operating-points-v2 = <0x0c>;
			cpu-supply = <0x0d>;
			phandle = <0x03>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x00 0x02>;
			enable-method = "psci";
			next-level-cache = <0x08>;
			capacity-dmips-mhz = <0x1e5>;
			clocks = <0x09 0x08>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x64>;
			cpu-idle-states = <0x0a 0x0b>;
			operating-points-v2 = <0x0c>;
			cpu-supply = <0x0d>;
			phandle = <0x04>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x00 0x03>;
			enable-method = "psci";
			next-level-cache = <0x08>;
			capacity-dmips-mhz = <0x1e5>;
			clocks = <0x09 0x08>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x64>;
			cpu-idle-states = <0x0a 0x0b>;
			operating-points-v2 = <0x0c>;
			cpu-supply = <0x0d>;
			phandle = <0x05>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x00 0x100>;
			enable-method = "psci";
			next-level-cache = <0x0e>;
			capacity-dmips-mhz = <0x400>;
			clocks = <0x09 0x09>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x1b4>;
			cpu-idle-states = <0x0a 0x0b>;
			operating-points-v2 = <0x0f>;
			cpu-supply = <0x10>;
			phandle = <0x06>;

			thermal-idle {
				#cooling-cells = <0x02>;
				duration-us = <0x2710>;
				exit-latency-us = <0x1f4>;
			};
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x00 0x101>;
			enable-method = "psci";
			next-level-cache = <0x0e>;
			capacity-dmips-mhz = <0x400>;
			clocks = <0x09 0x09>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x1b4>;
			cpu-idle-states = <0x0a 0x0b>;
			operating-points-v2 = <0x0f>;
			cpu-supply = <0x10>;
			phandle = <0x07>;

			thermal-idle {
				#cooling-cells = <0x02>;
				duration-us = <0x2710>;
				exit-latency-us = <0x1f4>;
			};
		};

		l2-cache0 {
			compatible = "cache";
			cache-level = <0x02>;
			cache-unified;
			phandle = <0x08>;
		};

		l2-cache1 {
			compatible = "cache";
			cache-level = <0x02>;
			cache-unified;
			phandle = <0x0e>;
		};

		idle-states {
			entry-method = "psci";

			cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x10000>;
				entry-latency-us = <0x78>;
				exit-latency-us = <0xfa>;
				min-residency-us = <0x384>;
				phandle = <0x0a>;
			};

			cluster-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <0x190>;
				exit-latency-us = <0x1f4>;
				min-residency-us = <0x7d0>;
				phandle = <0x0b>;
			};
		};
	};

	display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <0x11 0x12>;
	};

	memory-controller {
		compatible = "rockchip,rk3399-dmc";
		rockchip,pmu = <0x13>;
		devfreq-events = <0x14>;
		clocks = <0x09 0xa8>;
		clock-names = "dmc_clk";
		status = "okay";
		operating-points-v2 = <0x15>;
		bootph-all;
		interrupts = <0x00 0x01 0x04 0x00>;
		reg = <0x00 0xffa80000 0x00 0x800 0x00 0xffa80800 0x00 0x1800 0x00 0xffa82000 0x00 0x2000 0x00 0xffa84000 0x00 0x1000 0x00 0xffa88000 0x00 0x800 0x00 0xffa88800 0x00 0x1800 0x00 0xffa8a000 0x00 0x2000 0x00 0xffa8c000 0x00 0x1000>;
		rockchip,sdram-params = <0x02 0x0a 0x03 0x02 0x01 0x00 0x0f 0x0f 0x0f 0x0f 0x01 0x80241d22 0x15050f08 0x602 0x2122 0x4c 0x00 0x02 0x0a 0x03 0x02 0x01 0x00 0x0f 0x0f 0x0f 0x0f 0x01 0x80241d22 0x15050f08 0x602 0x2122 0x4c 0x00 0x32 0x07 0x02 0x0d 0x01 0xb00 0x00 0x00 0x00 0x00 0x13880 0xc3500 0x05 0x320 0x2d976 0x1c7e96 0x05 0x74c 0x2710 0x186a0 0x05 0x1000064 0x00 0x2020101 0x102 0x50 0xc8 0x00 0x6140000 0xa2800 0x400040c 0x1a042008 0x10080a11 0x283c0a00 0x26110c 0xa030704 0x8000204 0xa0a 0x40036b0 0xe0e0804 0x8007fa7 0xa0a0808 0x40006d6 0x2030404 0x110a0800 0x8040413 0x1400640a 0x2010a0a 0x10001 0x4082713 0x41409 0x00 0x3010000 0x6100070 0xe310106 0xbb000e 0x00 0x80005 0xa0005 0xa0017 0x107140b 0x30a0505 0xe080502 0x5050103 0x73030a 0x10e0073 0xf010e 0x505000f 0x3030605 0x8080301 0x8030f08 0x5050302 0x3030305 0x301 0x301 0x01 0x00 0x00 0x1000000 0x80104002 0x40003 0x40005 0x30000 0x50004 0x04 0x40003 0x40005 0x18400000 0xc20 0x1c6238c4 0x2ec0000 0x176 0x00 0x00 0x00 0x00 0x00 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0x20003 0x00 0x00 0x00 0x2a 0x15 0x15 0x2a 0x33 0x0c 0x0c 0x33 0x1ee6b16a 0x10000000 0x00 0x30055 0x3000300 0x3000300 0xc0300 0x42080010 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x4000f01 0x20040 0x20055 0x00 0x00 0x00 0x50 0x00 0x1010100 0x600 0x00 0x6400 0x9221902 0x00 0xd1f01 0xd1f0d1f 0xd1f0d1f 0x30003 0x3000300 0x300 0x9221902 0x00 0x00 0x1020000 0x01 0x411 0x411 0x40 0x40 0x411 0x411 0x4410 0x4410 0x4410 0x4410 0x4410 0x411 0x4410 0x411 0x4410 0x411 0x4410 0x00 0x00 0x00 0x64000000 0x00 0x00 0x108 0x00 0x00 0x00 0x00 0x00 0x00 0xe4000000 0x00 0x00 0x1010000 0x00>;
	};

	pmu_a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <0x01 0x07 0x08 0x16>;
	};

	pmu_a72 {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <0x01 0x07 0x08 0x17>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <0x01 0x0d 0x08 0x00 0x01 0x0e 0x08 0x00 0x01 0x0b 0x08 0x00 0x01 0x0a 0x08 0x00>;
		arm,no-tick-in-suspend;
	};

	xin24m {
		compatible = "fixed-clock";
		clock-frequency = <0x16e3600>;
		clock-output-names = "xin24m";
		#clock-cells = <0x00>;
		phandle = <0x99>;
	};

	pcie@f8000000 {
		compatible = "rockchip,rk3399-pcie";
		reg = <0x00 0xf8000000 0x00 0x2000000 0x00 0xfd000000 0x00 0x1000000>;
		reg-names = "axi-base\0apb-base";
		device_type = "pci";
		#address-cells = <0x03>;
		#size-cells = <0x02>;
		#interrupt-cells = <0x01>;
		aspm-no-l0s;
		bus-range = <0x00 0x1f>;
		clocks = <0x09 0xc5 0x09 0xc4 0x09 0x147 0x09 0xa0>;
		clock-names = "aclk\0aclk-perf\0hclk\0pm";
		interrupts = <0x00 0x31 0x04 0x00 0x00 0x32 0x04 0x00 0x00 0x33 0x04 0x00>;
		interrupt-names = "sys\0legacy\0client";
		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
		interrupt-map = <0x00 0x00 0x00 0x01 0x18 0x00 0x00 0x00 0x00 0x02 0x18 0x01 0x00 0x00 0x00 0x03 0x18 0x02 0x00 0x00 0x00 0x04 0x18 0x03>;
		max-link-speed = <0x01>;
		msi-map = <0x00 0x19 0x00 0x1000>;
		phys = <0x1a 0x00 0x1a 0x01 0x1a 0x02 0x1a 0x03>;
		phy-names = "pcie-phy-0\0pcie-phy-1\0pcie-phy-2\0pcie-phy-3";
		ranges = <0x82000000 0x00 0xfa000000 0x00 0xfa000000 0x00 0x1e00000 0x81000000 0x00 0xfbe00000 0x00 0xfbe00000 0x00 0x100000>;
		resets = <0x09 0x82 0x09 0x83 0x09 0x84 0x09 0x85 0x09 0x86 0x09 0x81 0x09 0x80>;
		reset-names = "core\0mgmt\0mgmt-sticky\0pipe\0pm\0pclk\0aclk";
		status = "okay";
		ep-gpios = <0x1b 0x19 0x00>;
		num-lanes = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x1c>;
		vpcie3v3-supply = <0x1d>;
		vpcie1v8-supply = <0x1e>;
		vpcie0v9-supply = <0x1f>;

		interrupt-controller {
			interrupt-controller;
			#address-cells = <0x00>;
			#interrupt-cells = <0x01>;
			phandle = <0x18>;
		};
	};

	ethernet@fe300000 {
		compatible = "rockchip,rk3399-gmac";
		reg = <0x00 0xfe300000 0x00 0x10000>;
		interrupts = <0x00 0x0c 0x04 0x00>;
		interrupt-names = "macirq";
		clocks = <0x09 0x69 0x09 0x67 0x09 0x68 0x09 0x66 0x09 0x6a 0x09 0xd5 0x09 0x166>;
		clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_ref\0clk_mac_refout\0aclk_mac\0pclk_mac";
		power-domains = <0x20 0x16>;
		resets = <0x09 0x89>;
		reset-names = "stmmaceth";
		rockchip,grf = <0x21>;
		snps,txpbl = <0x04>;
		status = "okay";
		assigned-clocks = <0x09 0xa6>;
		assigned-clock-parents = <0x22>;
		clock_in_out = "input";
		phy-supply = <0x23>;
		phy-mode = "rgmii";
		pinctrl-names = "default";
		pinctrl-0 = <0x24>;
		snps,reset-gpio = <0x25 0x0f 0x01>;
		snps,reset-active-low;
		snps,reset-delays-us = <0x00 0x2710 0xc350>;
		tx_delay = <0x28>;
		rx_delay = <0x11>;
	};

	mmc@fe310000 {
		compatible = "rockchip,rk3399-dw-mshc\0rockchip,rk3288-dw-mshc";
		reg = <0x00 0xfe310000 0x00 0x4000>;
		interrupts = <0x00 0x40 0x04 0x00>;
		max-frequency = <0x8f0d180>;
		clocks = <0x09 0x1ee 0x09 0x4d 0x09 0x9c 0x09 0x9d>;
		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
		fifo-depth = <0x100>;
		power-domains = <0x20 0x1c>;
		resets = <0x09 0x79>;
		reset-names = "reset";
		status = "disabled";
	};

	mmc@fe320000 {
		compatible = "rockchip,rk3399-dw-mshc\0rockchip,rk3288-dw-mshc";
		reg = <0x00 0xfe320000 0x00 0x4000>;
		interrupts = <0x00 0x41 0x04 0x00>;
		max-frequency = <0x8f0d180>;
		assigned-clocks = <0x09 0x1cd>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x09 0x1ce 0x09 0x4c 0x09 0x9a 0x09 0x9b>;
		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
		fifo-depth = <0x100>;
		power-domains = <0x20 0x1b>;
		resets = <0x09 0x7a>;
		reset-names = "reset";
		status = "okay";
		bus-width = <0x04>;
		cap-sd-highspeed;
		cd-gpios = <0x26 0x07 0x01>;
		disable-wp;
		pinctrl-names = "default";
		pinctrl-0 = <0x27 0x28 0x29 0x2a>;
		sd-uhs-sdr104;
		vmmc-supply = <0x2b>;
		vqmmc-supply = <0x2c>;
		bootph-all;
		u-boot,spl-fifo-mode;
	};

	mmc@fe330000 {
		compatible = "rockchip,rk3399-sdhci-5.1\0arasan,sdhci-5.1";
		reg = <0x00 0xfe330000 0x00 0x10000>;
		interrupts = <0x00 0x0b 0x04 0x00>;
		arasan,soc-ctl-syscon = <0x21>;
		assigned-clocks = <0x09 0x4e>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x09 0x4e 0x09 0xf0>;
		clock-names = "clk_xin\0clk_ahb";
		clock-output-names = "emmc_cardclock";
		#clock-cells = <0x00>;
		phys = <0x2d>;
		phy-names = "phy_arasan";
		power-domains = <0x20 0x17>;
		disable-cqe-dcmd;
		status = "okay";
		bus-width = <0x08>;
		mmc-hs400-1_8v;
		mmc-hs400-enhanced-strobe;
		vmmc-supply = <0x2e>;
		vqmmc-supply = <0x2e>;
		max-frequency = <0xbebc200>;
		bootph-all;
		u-boot,spl-fifo-mode;
		phandle = <0x9d>;
	};

	usb@fe380000 {
		compatible = "generic-ehci";
		reg = <0x00 0xfe380000 0x00 0x20000>;
		interrupts = <0x00 0x1a 0x04 0x00>;
		clocks = <0x09 0x1c8 0x09 0x1c9 0x2f>;
		phys = <0x30>;
		phy-names = "usb";
		status = "okay";
	};

	usb@fe3a0000 {
		compatible = "generic-ohci";
		reg = <0x00 0xfe3a0000 0x00 0x20000>;
		interrupts = <0x00 0x1c 0x04 0x00>;
		clocks = <0x09 0x1c8 0x09 0x1c9 0x2f>;
		phys = <0x30>;
		phy-names = "usb";
		status = "okay";
	};

	usb@fe3c0000 {
		compatible = "generic-ehci";
		reg = <0x00 0xfe3c0000 0x00 0x20000>;
		interrupts = <0x00 0x1e 0x04 0x00>;
		clocks = <0x09 0x1ca 0x09 0x1cb 0x31>;
		phys = <0x32>;
		phy-names = "usb";
		status = "okay";
	};

	usb@fe3e0000 {
		compatible = "generic-ohci";
		reg = <0x00 0xfe3e0000 0x00 0x20000>;
		interrupts = <0x00 0x20 0x04 0x00>;
		clocks = <0x09 0x1ca 0x09 0x1cb 0x31>;
		phys = <0x32>;
		phy-names = "usb";
		status = "okay";
	};

	debug@fe430000 {
		compatible = "arm,coresight-cpu-debug\0arm,primecell";
		reg = <0x00 0xfe430000 0x00 0x1000>;
		clocks = <0x09 0x14d>;
		clock-names = "apb_pclk";
		cpu = <0x02>;
	};

	debug@fe432000 {
		compatible = "arm,coresight-cpu-debug\0arm,primecell";
		reg = <0x00 0xfe432000 0x00 0x1000>;
		clocks = <0x09 0x14d>;
		clock-names = "apb_pclk";
		cpu = <0x03>;
	};

	debug@fe434000 {
		compatible = "arm,coresight-cpu-debug\0arm,primecell";
		reg = <0x00 0xfe434000 0x00 0x1000>;
		clocks = <0x09 0x14d>;
		clock-names = "apb_pclk";
		cpu = <0x04>;
	};

	debug@fe436000 {
		compatible = "arm,coresight-cpu-debug\0arm,primecell";
		reg = <0x00 0xfe436000 0x00 0x1000>;
		clocks = <0x09 0x14d>;
		clock-names = "apb_pclk";
		cpu = <0x05>;
	};

	debug@fe610000 {
		compatible = "arm,coresight-cpu-debug\0arm,primecell";
		reg = <0x00 0xfe610000 0x00 0x1000>;
		clocks = <0x09 0x14c>;
		clock-names = "apb_pclk";
		cpu = <0x06>;
	};

	debug@fe710000 {
		compatible = "arm,coresight-cpu-debug\0arm,primecell";
		reg = <0x00 0xfe710000 0x00 0x1000>;
		clocks = <0x09 0x14c>;
		clock-names = "apb_pclk";
		cpu = <0x07>;
	};

	usb@fe800000 {
		compatible = "rockchip,rk3399-dwc3";
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		clocks = <0x09 0x81 0x09 0x83 0x09 0xf6 0x09 0xf8 0x09 0xf4 0x09 0xf9>;
		clock-names = "ref_clk\0suspend_clk\0bus_clk\0aclk_usb3_rksoc_axi_perf\0aclk_usb3\0grf_clk";
		resets = <0x09 0x125>;
		reset-names = "usb3-otg";
		status = "okay";

		usb@fe800000 {
			compatible = "snps,dwc3";
			reg = <0x00 0xfe800000 0x00 0x100000>;
			interrupts = <0x00 0x69 0x04 0x00>;
			clocks = <0x09 0x81 0x09 0xf6 0x09 0x83>;
			clock-names = "ref\0bus_early\0suspend";
			dr_mode = "otg";
			phys = <0x33 0x34>;
			phy-names = "usb2-phy\0usb3-phy";
			phy_type = "utmi_wide";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			power-domains = <0x20 0x18>;
			status = "okay";
		};
	};

	usb@fe900000 {
		compatible = "rockchip,rk3399-dwc3";
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		clocks = <0x09 0x82 0x09 0x84 0x09 0xf7 0x09 0xf8 0x09 0xf4 0x09 0xf9>;
		clock-names = "ref_clk\0suspend_clk\0bus_clk\0aclk_usb3_rksoc_axi_perf\0aclk_usb3\0grf_clk";
		resets = <0x09 0x126>;
		reset-names = "usb3-otg";
		status = "okay";

		usb@fe900000 {
			compatible = "snps,dwc3";
			reg = <0x00 0xfe900000 0x00 0x100000>;
			interrupts = <0x00 0x6e 0x04 0x00>;
			clocks = <0x09 0x82 0x09 0xf7 0x09 0x84>;
			clock-names = "ref\0bus_early\0suspend";
			dr_mode = "host";
			phys = <0x35 0x36>;
			phy-names = "usb2-phy\0usb3-phy";
			phy_type = "utmi_wide";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			power-domains = <0x20 0x18>;
			status = "okay";
		};
	};

	dp@fec00000 {
		compatible = "rockchip,rk3399-cdn-dp";
		reg = <0x00 0xfec00000 0x00 0x100000>;
		interrupts = <0x00 0x09 0x04 0x00>;
		assigned-clocks = <0x09 0x72 0x09 0xa1>;
		assigned-clock-rates = <0x5f5e100 0xbebc200>;
		clocks = <0x09 0x72 0x09 0x175 0x09 0xa1 0x09 0x16f>;
		clock-names = "core-clk\0pclk\0spdif\0grf";
		phys = <0x37 0x38>;
		power-domains = <0x20 0x15>;
		resets = <0x09 0x103 0x09 0x148 0x09 0x14a 0x09 0xfd>;
		reset-names = "spdif\0dptx\0apb\0core";
		rockchip,grf = <0x21>;
		#sound-dai-cells = <0x01>;
		status = "disabled";

		ports {

			port {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x39>;
					phandle = <0xb1>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0x3a>;
					phandle = <0xab>;
				};
			};
		};
	};

	interrupt-controller@fee00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <0x04>;
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		interrupt-controller;
		reg = <0x00 0xfee00000 0x00 0x10000 0x00 0xfef00000 0x00 0xc0000 0x00 0xfff00000 0x00 0x10000 0x00 0xfff10000 0x00 0x10000 0x00 0xfff20000 0x00 0x10000>;
		interrupts = <0x01 0x09 0x04 0x00>;
		phandle = <0x01>;

		msi-controller@fee20000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <0x01>;
			reg = <0x00 0xfee20000 0x00 0x20000>;
			phandle = <0x19>;
		};

		ppi-partitions {

			interrupt-partition-0 {
				affinity = <0x02 0x03 0x04 0x05>;
				phandle = <0x16>;
			};

			interrupt-partition-1 {
				affinity = <0x06 0x07>;
				phandle = <0x17>;
			};
		};
	};

	saradc@ff100000 {
		compatible = "rockchip,rk3399-saradc";
		reg = <0x00 0xff100000 0x00 0x100>;
		interrupts = <0x00 0x3e 0x04 0x00>;
		#io-channel-cells = <0x01>;
		clocks = <0x09 0x50 0x09 0x165>;
		clock-names = "saradc\0apb_pclk";
		resets = <0x09 0xd4>;
		reset-names = "saradc-apb";
		status = "okay";
		vref-supply = <0x3b>;
		phandle = <0xcd>;
	};

	crypto@ff8b0000 {
		compatible = "rockchip,rk3399-crypto";
		reg = <0x00 0xff8b0000 0x00 0x4000>;
		interrupts = <0x00 0x00 0x04 0x00>;
		clocks = <0x09 0x1d0 0x09 0x1d2 0x09 0x85>;
		clock-names = "hclk_master\0hclk_slave\0sclk";
		resets = <0x09 0xb5 0x09 0xae 0x09 0xaf>;
		reset-names = "master\0slave\0crypto-rst";
	};

	crypto@ff8b8000 {
		compatible = "rockchip,rk3399-crypto\0rockchip,cryptov1-rng";
		reg = <0x00 0xff8b8000 0x00 0x4000>;
		interrupts = <0x00 0x87 0x04 0x00>;
		clocks = <0x09 0x1d1 0x09 0x1d3 0x09 0x86>;
		clock-names = "hclk_master\0hclk_slave\0sclk";
		resets = <0x09 0xba 0x09 0xb8 0x09 0xb9>;
		reset-names = "master\0slave\0crypto-rst";
	};

	i2c@ff110000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff110000 0x00 0x1000>;
		assigned-clocks = <0x09 0x41>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x09 0x41 0x09 0x155>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x3b 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x3c>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		i2c-scl-rising-time-ns = <0x12c>;
		i2c-scl-falling-time-ns = <0x0f>;
	};

	i2c@ff120000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff120000 0x00 0x1000>;
		assigned-clocks = <0x09 0x42>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x09 0x42 0x09 0x156>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x23 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x3d>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	i2c@ff130000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff130000 0x00 0x1000>;
		assigned-clocks = <0x09 0x43>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x09 0x43 0x09 0x157>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x22 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x3e>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		i2c-scl-rising-time-ns = <0x1c2>;
		i2c-scl-falling-time-ns = <0x0f>;
		phandle = <0xba>;
	};

	i2c@ff140000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff140000 0x00 0x1000>;
		assigned-clocks = <0x09 0x44>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x09 0x44 0x09 0x158>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x26 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x3f>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	i2c@ff150000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff150000 0x00 0x1000>;
		assigned-clocks = <0x09 0x45>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x09 0x45 0x09 0x159>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x25 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x40>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	i2c@ff160000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff160000 0x00 0x1000>;
		assigned-clocks = <0x09 0x46>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x09 0x46 0x09 0x15a>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x24 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x41>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		clock-frequency = <0x61a80>;
		i2c-scl-rising-time-ns = <0x159>;
		i2c-scl-falling-time-ns = <0x0b>;

		usb-typec@22 {
			compatible = "fcs,fusb302";
			reg = <0x22>;
			interrupt-parent = <0x42>;
			interrupts = <0x02 0x08>;
			pinctrl-names = "default";
			pinctrl-0 = <0x43>;
			vbus-supply = <0x44>;
			status = "okay";

			connector {
				compatible = "usb-c-connector";
				data-role = "dual";
				label = "USB-C0";
				power-role = "sink";
				op-sink-microwatt = <0xe4e1c0>;
				sink-pdos = <0x601912c 0x602d0c8 0x603c096 0x604b078 0x606405a 0x9901912c 0xc190323c 0x59019048>;

				ports {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					port@0 {
						reg = <0x00>;

						endpoint {
							remote-endpoint = <0x45>;
							phandle = <0x9b>;
						};
					};

					port@1 {
						reg = <0x01>;

						endpoint {
							remote-endpoint = <0x46>;
							phandle = <0x9f>;
						};
					};

					port@2 {
						reg = <0x02>;

						endpoint {
							remote-endpoint = <0x47>;
							phandle = <0x9e>;
						};
					};
				};
			};
		};
	};

	serial@ff180000 {
		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
		reg = <0x00 0xff180000 0x00 0x100>;
		clocks = <0x09 0x51 0x09 0x160>;
		clock-names = "baudclk\0apb_pclk";
		interrupts = <0x00 0x63 0x04 0x00>;
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x48 0x49>;
		status = "okay";
		bootph-all;
	};

	serial@ff190000 {
		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
		reg = <0x00 0xff190000 0x00 0x100>;
		clocks = <0x09 0x52 0x09 0x161>;
		clock-names = "baudclk\0apb_pclk";
		interrupts = <0x00 0x62 0x04 0x00>;
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x4a>;
		status = "disabled";
	};

	serial@ff1a0000 {
		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
		reg = <0x00 0xff1a0000 0x00 0x100>;
		clocks = <0x09 0x53 0x09 0x162>;
		clock-names = "baudclk\0apb_pclk";
		interrupts = <0x00 0x64 0x04 0x00>;
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x4b>;
		status = "okay";
		bootph-all;
	};

	serial@ff1b0000 {
		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
		reg = <0x00 0xff1b0000 0x00 0x100>;
		clocks = <0x09 0x54 0x09 0x163>;
		clock-names = "baudclk\0apb_pclk";
		interrupts = <0x00 0x65 0x04 0x00>;
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x4c>;
		status = "disabled";
	};

	spi@ff1c0000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff1c0000 0x00 0x1000>;
		clocks = <0x09 0x47 0x09 0x15b>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x44 0x04 0x00>;
		dmas = <0x4d 0x0a 0x4d 0x0b>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x4e 0x4f 0x50 0x51>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	spi@ff1d0000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff1d0000 0x00 0x1000>;
		clocks = <0x09 0x48 0x09 0x15c>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x35 0x04 0x00>;
		dmas = <0x4d 0x0c 0x4d 0x0d>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x52 0x53 0x54 0x55>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		bootph-all;

		flash@0 {
			compatible = "jedec,spi-nor";
			reg = <0x00>;
			spi-max-frequency = <0x1c9c380>;
			bootph-all;
		};
	};

	spi@ff1e0000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff1e0000 0x00 0x1000>;
		clocks = <0x09 0x49 0x09 0x15d>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x34 0x04 0x00>;
		dmas = <0x4d 0x0e 0x4d 0x0f>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x56 0x57 0x58 0x59>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	spi@ff1f0000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff1f0000 0x00 0x1000>;
		clocks = <0x09 0x4a 0x09 0x15e>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x43 0x04 0x00>;
		dmas = <0x4d 0x12 0x4d 0x13>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x5a 0x5b 0x5c 0x5d>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	spi@ff200000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff200000 0x00 0x1000>;
		clocks = <0x09 0x4b 0x09 0x15f>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x84 0x04 0x00>;
		dmas = <0x5e 0x08 0x5e 0x09>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x5f 0x60 0x61 0x62>;
		power-domains = <0x20 0x1c>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	thermal-zones {

		cpu-thermal {
			polling-delay-passive = <0x64>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x63 0x00>;

			trips {

				cpu_alert0 {
					temperature = <0xfde8>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x64>;
				};

				cpu_alert1 {
					temperature = <0x11170>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x65>;
				};

				cpu_crit {
					temperature = <0x13880>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};

			cooling-maps {

				map0 {
					trip = <0x64>;
					cooling-device = <0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff>;
				};

				map1 {
					trip = <0x65>;
					cooling-device = <0x02 0xffffffff 0xffffffff 0x03 0xffffffff 0xffffffff 0x04 0xffffffff 0xffffffff 0x05 0xffffffff 0xffffffff 0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff>;
				};
			};
		};

		gpu-thermal {
			polling-delay-passive = <0x64>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x63 0x01>;

			trips {

				gpu_alert0 {
					temperature = <0x11170>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x66>;
				};

				gpu_crit {
					temperature = <0x13880>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};

			cooling-maps {

				map0 {
					trip = <0x66>;
					cooling-device = <0x67 0xffffffff 0xffffffff>;
				};
			};
		};
	};

	tsadc@ff260000 {
		compatible = "rockchip,rk3399-tsadc";
		reg = <0x00 0xff260000 0x00 0x100>;
		interrupts = <0x00 0x61 0x04 0x00>;
		assigned-clocks = <0x09 0x4f>;
		assigned-clock-rates = <0xb71b0>;
		clocks = <0x09 0x4f 0x09 0x164>;
		clock-names = "tsadc\0apb_pclk";
		resets = <0x09 0xe8>;
		reset-names = "tsadc-apb";
		rockchip,grf = <0x21>;
		rockchip,hw-tshut-temp = <0x17318>;
		pinctrl-names = "init\0default\0sleep";
		pinctrl-0 = <0x68>;
		pinctrl-1 = <0x69>;
		pinctrl-2 = <0x68>;
		#thermal-sensor-cells = <0x01>;
		status = "okay";
		rockchip,hw-tshut-mode = <0x01>;
		rockchip,hw-tshut-polarity = <0x01>;
		phandle = <0x63>;
	};

	qos@ffa58000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa58000 0x00 0x20>;
		phandle = <0x71>;
	};

	qos@ffa5c000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa5c000 0x00 0x20>;
		phandle = <0x72>;
	};

	qos@ffa60080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa60080 0x00 0x20>;
	};

	qos@ffa60100 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa60100 0x00 0x20>;
	};

	qos@ffa60180 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa60180 0x00 0x20>;
	};

	qos@ffa70000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa70000 0x00 0x20>;
		phandle = <0x75>;
	};

	qos@ffa70080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa70080 0x00 0x20>;
		phandle = <0x76>;
	};

	qos@ffa74000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa74000 0x00 0x20>;
		phandle = <0x73>;
	};

	qos@ffa76000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa76000 0x00 0x20>;
		phandle = <0x74>;
	};

	qos@ffa90000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa90000 0x00 0x20>;
		phandle = <0x77>;
	};

	qos@ffa98000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa98000 0x00 0x20>;
		phandle = <0x6a>;
	};

	qos@ffaa0000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffaa0000 0x00 0x20>;
		phandle = <0x78>;
	};

	qos@ffaa0080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffaa0080 0x00 0x20>;
		phandle = <0x79>;
	};

	qos@ffaa8000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffaa8000 0x00 0x20>;
		phandle = <0x7a>;
	};

	qos@ffaa8080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffaa8080 0x00 0x20>;
		phandle = <0x7b>;
	};

	qos@ffab0000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffab0000 0x00 0x20>;
		phandle = <0x6b>;
	};

	qos@ffab0080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffab0080 0x00 0x20>;
		phandle = <0x6c>;
	};

	qos@ffab8000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffab8000 0x00 0x20>;
		phandle = <0x6d>;
	};

	qos@ffac0000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffac0000 0x00 0x20>;
		phandle = <0x6e>;
	};

	qos@ffac0080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffac0080 0x00 0x20>;
		phandle = <0x6f>;
	};

	qos@ffac8000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffac8000 0x00 0x20>;
		phandle = <0x7c>;
	};

	qos@ffac8080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffac8080 0x00 0x20>;
		phandle = <0x7d>;
	};

	qos@ffad0000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffad0000 0x00 0x20>;
		phandle = <0x7e>;
	};

	qos@ffad8080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffad8080 0x00 0x20>;
	};

	qos@ffae0000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffae0000 0x00 0x20>;
		phandle = <0x70>;
	};

	power-management@ff310000 {
		compatible = "rockchip,rk3399-pmu\0syscon\0simple-mfd";
		reg = <0x00 0xff310000 0x00 0x1000>;
		bootph-all;

		power-controller {
			compatible = "rockchip,rk3399-power-controller";
			#power-domain-cells = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x20>;

			power-domain@34 {
				reg = <0x22>;
				clocks = <0x09 0xe1 0x09 0x1dd>;
				pm_qos = <0x6a>;
				#power-domain-cells = <0x00>;
			};

			power-domain@33 {
				reg = <0x21>;
				clocks = <0x09 0xdc 0x09 0x1e5>;
				pm_qos = <0x6b 0x6c>;
				#power-domain-cells = <0x00>;
			};

			power-domain@31 {
				reg = <0x1f>;
				clocks = <0x09 0xeb 0x09 0x1ea>;
				pm_qos = <0x6d>;
				#power-domain-cells = <0x00>;
			};

			power-domain@32 {
				reg = <0x20>;
				clocks = <0x09 0xed 0x09 0x1ec 0x09 0x9f 0x09 0x9e>;
				pm_qos = <0x6e 0x6f>;
				#power-domain-cells = <0x00>;
			};

			power-domain@35 {
				reg = <0x23>;
				clocks = <0x09 0xd0>;
				pm_qos = <0x70>;
				#power-domain-cells = <0x00>;
			};

			power-domain@25 {
				reg = <0x19>;
				clocks = <0x09 0x16c>;
				#power-domain-cells = <0x00>;
			};

			power-domain@23 {
				reg = <0x17>;
				clocks = <0x09 0xf0>;
				pm_qos = <0x71>;
				#power-domain-cells = <0x00>;
			};

			power-domain@22 {
				reg = <0x16>;
				clocks = <0x09 0xd5 0x09 0x166>;
				pm_qos = <0x72>;
				#power-domain-cells = <0x00>;
			};

			power-domain@27 {
				reg = <0x1b>;
				clocks = <0x09 0x1ce 0x09 0x4c>;
				pm_qos = <0x73>;
				#power-domain-cells = <0x00>;
			};

			power-domain@28 {
				reg = <0x1c>;
				clocks = <0x09 0x1ee>;
				pm_qos = <0x74>;
				#power-domain-cells = <0x00>;
			};

			power-domain@8 {
				reg = <0x08>;
				clocks = <0x09 0x7e 0x09 0x7d>;
				#power-domain-cells = <0x00>;
			};

			power-domain@9 {
				reg = <0x09>;
				clocks = <0x09 0x80 0x09 0x7f>;
				#power-domain-cells = <0x00>;
			};

			power-domain@24 {
				reg = <0x18>;
				clocks = <0x09 0xf4>;
				pm_qos = <0x75 0x76>;
				#power-domain-cells = <0x00>;
			};

			power-domain@15 {
				reg = <0x0f>;
				#power-domain-cells = <0x01>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				power-domain@21 {
					reg = <0x15>;
					clocks = <0x09 0xde 0x09 0x1e7 0x09 0x172>;
					pm_qos = <0x77>;
					#power-domain-cells = <0x00>;
				};

				power-domain@19 {
					reg = <0x13>;
					clocks = <0x09 0xe5 0x09 0x1df>;
					pm_qos = <0x78 0x79>;
					#power-domain-cells = <0x00>;
				};

				power-domain@20 {
					reg = <0x14>;
					clocks = <0x09 0xe6 0x09 0x1e0>;
					pm_qos = <0x7a 0x7b>;
					#power-domain-cells = <0x00>;
				};

				power-domain@16 {
					reg = <0x10>;
					#power-domain-cells = <0x01>;
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					power-domain@17 {
						reg = <0x11>;
						clocks = <0x09 0xd9 0x09 0x1d9>;
						pm_qos = <0x7c 0x7d>;
						#power-domain-cells = <0x00>;
					};

					power-domain@18 {
						reg = <0x12>;
						clocks = <0x09 0xdb 0x09 0x1db>;
						pm_qos = <0x7e>;
						#power-domain-cells = <0x00>;
					};
				};
			};
		};
	};

	syscon@ff320000 {
		compatible = "rockchip,rk3399-pmugrf\0syscon\0simple-mfd";
		reg = <0x00 0xff320000 0x00 0x1000>;
		bootph-all;
		phandle = <0x13>;

		io-domains {
			compatible = "rockchip,rk3399-pmu-io-voltage-domain";
			status = "okay";
			pmu1830-supply = <0x7f>;
		};
	};

	spi@ff350000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff350000 0x00 0x1000>;
		clocks = <0x80 0x03 0x80 0x1f>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x3c 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x81 0x82 0x83 0x84>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	serial@ff370000 {
		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
		reg = <0x00 0xff370000 0x00 0x100>;
		clocks = <0x80 0x06 0x80 0x22>;
		clock-names = "baudclk\0apb_pclk";
		interrupts = <0x00 0x66 0x04 0x00>;
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x85>;
		status = "disabled";
	};

	i2c@ff3c0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff3c0000 0x00 0x1000>;
		assigned-clocks = <0x80 0x09>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x80 0x09 0x80 0x1b>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x39 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x86>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		clock-frequency = <0x61a80>;
		i2c-scl-rising-time-ns = <0xa8>;
		i2c-scl-falling-time-ns = <0x04>;

		pmic@1b {
			compatible = "rockchip,rk808";
			reg = <0x1b>;
			interrupt-parent = <0x42>;
			interrupts = <0x15 0x08>;
			#clock-cells = <0x01>;
			clock-output-names = "xin32k\0rk808-clkout2";
			pinctrl-names = "default";
			pinctrl-0 = <0x87>;
			rockchip,system-power-controller;
			wakeup-source;
			vcc1-supply = <0x88>;
			vcc2-supply = <0x88>;
			vcc3-supply = <0x88>;
			vcc4-supply = <0x88>;
			vcc6-supply = <0x88>;
			vcc7-supply = <0x88>;
			vcc8-supply = <0x88>;
			vcc9-supply = <0x88>;
			vcc10-supply = <0x88>;
			vcc11-supply = <0x88>;
			vcc12-supply = <0x88>;
			vddio-supply = <0x7f>;
			phandle = <0xd4>;

			regulators {

				DCDC_REG1 {
					regulator-name = "vdd_center";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xb71b0>;
					regulator-max-microvolt = <0x149970>;
					regulator-ramp-delay = <0x1771>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				DCDC_REG2 {
					regulator-name = "vdd_cpu_l";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xb71b0>;
					regulator-max-microvolt = <0x149970>;
					regulator-ramp-delay = <0x1771>;
					phandle = <0x0d>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				DCDC_REG3 {
					regulator-name = "vcc_ddr";
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-on-in-suspend;
					};
				};

				DCDC_REG4 {
					regulator-name = "vcc_1v8";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					phandle = <0x2e>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x1b7740>;
					};
				};

				LDO_REG1 {
					regulator-name = "vcca1v8_codec";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					phandle = <0x9a>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG2 {
					regulator-name = "vcca1v8_hdmi";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					phandle = <0xb9>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG3 {
					regulator-name = "vcc1v8_pmu";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					phandle = <0x1e>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x1b7740>;
					};
				};

				LDO_REG4 {
					regulator-name = "vcc_sdio";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x2dc6c0>;
					phandle = <0x2c>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x2dc6c0>;
					};
				};

				LDO_REG5 {
					regulator-name = "vcca3v0_codec";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x2dc6c0>;
					regulator-max-microvolt = <0x2dc6c0>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG6 {
					regulator-name = "vcc_1v5";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x16e360>;
					regulator-max-microvolt = <0x16e360>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x16e360>;
					};
				};

				LDO_REG7 {
					regulator-name = "vcca0v9_hdmi";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xdbba0>;
					regulator-max-microvolt = <0xdbba0>;
					phandle = <0xb8>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG8 {
					regulator-name = "vcc_3v0";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x2dc6c0>;
					regulator-max-microvolt = <0x2dc6c0>;
					phandle = <0x7f>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x2dc6c0>;
					};
				};

				SWITCH_REG1 {
					regulator-name = "vcc3v3_s3";
					regulator-always-on;
					regulator-boot-on;
					phandle = <0x23>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				SWITCH_REG2 {
					regulator-name = "vcc3v3_s0";
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};
			};
		};

		regulator@40 {
			compatible = "silergy,syr827";
			reg = <0x40>;
			fcs,suspend-voltage-selector = <0x01>;
			pinctrl-names = "default";
			pinctrl-0 = <0x89>;
			regulator-name = "vdd_cpu_b";
			regulator-min-microvolt = <0xadf34>;
			regulator-max-microvolt = <0x16e360>;
			regulator-ramp-delay = <0x3e8>;
			regulator-always-on;
			regulator-boot-on;
			vin-supply = <0x88>;
			phandle = <0x10>;

			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};

		regulator@41 {
			compatible = "silergy,syr828";
			reg = <0x41>;
			fcs,suspend-voltage-selector = <0x01>;
			pinctrl-names = "default";
			pinctrl-0 = <0x8a>;
			regulator-name = "vdd_gpu";
			regulator-min-microvolt = <0xadf34>;
			regulator-max-microvolt = <0x16e360>;
			regulator-ramp-delay = <0x3e8>;
			regulator-always-on;
			regulator-boot-on;
			vin-supply = <0x88>;
			phandle = <0xc6>;

			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};
	};

	i2c@ff3d0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff3d0000 0x00 0x1000>;
		assigned-clocks = <0x80 0x0a>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x80 0x0a 0x80 0x1c>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x38 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x8b>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		i2c-scl-rising-time-ns = <0x258>;
		i2c-scl-falling-time-ns = <0x14>;

		usb-typec@22 {
			compatible = "fcs,fusb302";
			reg = <0x22>;
			interrupt-parent = <0x42>;
			interrupts = <0x01 0x08>;
			pinctrl-names = "default";
			pinctrl-0 = <0x8c>;
			vbus-supply = <0x8d>;
			status = "okay";

			connector {
				compatible = "usb-c-connector";
				data-role = "dual";
				label = "USB-C1";
				power-role = "source";
				try-power-role = "source";
				source-pdos = <0xe01912c>;

				ports {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					port@0 {
						reg = <0x00>;

						endpoint {
							remote-endpoint = <0x8e>;
							phandle = <0x9c>;
						};
					};

					port@1 {
						reg = <0x01>;

						endpoint {
							remote-endpoint = <0x8f>;
							phandle = <0xa1>;
						};
					};

					port@2 {
						reg = <0x02>;

						endpoint {
							remote-endpoint = <0x90>;
							phandle = <0xa0>;
						};
					};
				};
			};
		};
	};

	i2c@ff3e0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff3e0000 0x00 0x1000>;
		assigned-clocks = <0x80 0x0b>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x80 0x0b 0x80 0x1d>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x3a 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x91>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	pwm@ff420000 {
		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
		reg = <0x00 0xff420000 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "default";
		pinctrl-0 = <0x92>;
		clocks = <0x80 0x1e>;
		status = "okay";
	};

	pwm@ff420010 {
		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
		reg = <0x00 0xff420010 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "default";
		pinctrl-0 = <0x93>;
		clocks = <0x80 0x1e>;
		status = "disabled";
	};

	pwm@ff420020 {
		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
		reg = <0x00 0xff420020 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "default";
		pinctrl-0 = <0x94>;
		clocks = <0x80 0x1e>;
		status = "okay";
		phandle = <0xdf>;
	};

	pwm@ff420030 {
		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
		reg = <0x00 0xff420030 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "default";
		pinctrl-0 = <0x95>;
		clocks = <0x80 0x1e>;
		status = "disabled";
	};

	dfi@ff630000 {
		reg = <0x00 0xff630000 0x00 0x4000>;
		compatible = "rockchip,rk3399-dfi";
		rockchip,pmu = <0x13>;
		interrupts = <0x00 0x83 0x04 0x00>;
		clocks = <0x09 0x179>;
		clock-names = "pclk_ddr_mon";
		status = "disabled";
		bootph-all;
		phandle = <0x14>;
	};

	video-codec@ff650000 {
		compatible = "rockchip,rk3399-vpu";
		reg = <0x00 0xff650000 0x00 0x800>;
		interrupts = <0x00 0x72 0x04 0x00 0x00 0x71 0x04 0x00>;
		interrupt-names = "vepu\0vdpu";
		clocks = <0x09 0xeb 0x09 0x1ea>;
		clock-names = "aclk\0hclk";
		iommus = <0x96>;
		power-domains = <0x20 0x1f>;
	};

	iommu@ff650800 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff650800 0x00 0x40>;
		interrupts = <0x00 0x73 0x04 0x00>;
		interrupt-names = "vpu_mmu";
		clocks = <0x09 0xeb 0x09 0x1ea>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		power-domains = <0x20 0x1f>;
		phandle = <0x96>;
	};

	video-codec@ff660000 {
		compatible = "rockchip,rk3399-vdec";
		reg = <0x00 0xff660000 0x00 0x480>;
		interrupts = <0x00 0x74 0x04 0x00>;
		clocks = <0x09 0xed 0x09 0x1ec 0x09 0x9f 0x09 0x9e>;
		clock-names = "axi\0ahb\0cabac\0core";
		iommus = <0x97>;
		power-domains = <0x20 0x20>;
		resets = <0x09 0x5b 0x09 0x59 0x09 0x5c 0x09 0x5d 0x09 0x58 0x09 0x5a>;
		reset-names = "video_h\0video_a\0video_core\0video_cabac\0niu_a\0niu_h";
	};

	iommu@ff660480 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff660480 0x00 0x40 0x00 0xff6604c0 0x00 0x40>;
		interrupts = <0x00 0x75 0x04 0x00>;
		interrupt-names = "vdec_mmu";
		clocks = <0x09 0xed 0x09 0x1ec>;
		clock-names = "aclk\0iface";
		power-domains = <0x20 0x20>;
		#iommu-cells = <0x00>;
		phandle = <0x97>;
	};

	iep@ff670000 {
		compatible = "rockchip,rk3399-iep\0rockchip,rk3228-iep";
		reg = <0x00 0xff670000 0x00 0x800>;
		interrupts = <0x00 0x2a 0x04 0x00>;
		interrupt-names = "iep";
		clocks = <0x09 0xe1 0x09 0x1dd>;
		clock-names = "axi\0ahb";
		power-domains = <0x20 0x22>;
		iommus = <0x98>;
	};

	iommu@ff670800 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff670800 0x00 0x40>;
		interrupts = <0x00 0x2a 0x04 0x00>;
		interrupt-names = "iep_mmu";
		clocks = <0x09 0xe1 0x09 0x1dd>;
		clock-names = "aclk\0iface";
		power-domains = <0x20 0x22>;
		#iommu-cells = <0x00>;
		status = "disabled";
		phandle = <0x98>;
	};

	rga@ff680000 {
		compatible = "rockchip,rk3399-rga";
		reg = <0x00 0xff680000 0x00 0x10000>;
		interrupts = <0x00 0x37 0x04 0x00>;
		clocks = <0x09 0xdc 0x09 0x1e5 0x09 0x6d>;
		clock-names = "aclk\0hclk\0sclk";
		resets = <0x09 0x6a 0x09 0x67 0x09 0x69>;
		reset-names = "core\0axi\0ahb";
		power-domains = <0x20 0x21>;
	};

	efuse@ff690000 {
		compatible = "rockchip,rk3399-efuse";
		reg = <0x00 0xff690000 0x00 0x80>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		clocks = <0x09 0x17d>;
		clock-names = "pclk_efuse";

		cpu-id@7 {
			reg = <0x07 0x10>;
		};

		cpu-leakage@17 {
			reg = <0x17 0x01>;
		};

		gpu-leakage@18 {
			reg = <0x18 0x01>;
		};

		center-leakage@19 {
			reg = <0x19 0x01>;
		};

		cpu-leakage@1a {
			reg = <0x1a 0x01>;
		};

		logic-leakage@1b {
			reg = <0x1b 0x01>;
		};

		wafer-info@1c {
			reg = <0x1c 0x01>;
		};
	};

	dma-controller@ff6d0000 {
		compatible = "arm,pl330\0arm,primecell";
		reg = <0x00 0xff6d0000 0x00 0x4000>;
		interrupts = <0x00 0x05 0x04 0x00 0x00 0x06 0x04 0x00>;
		#dma-cells = <0x01>;
		arm,pl330-periph-burst;
		clocks = <0x09 0xd3>;
		clock-names = "apb_pclk";
		phandle = <0x5e>;
	};

	dma-controller@ff6e0000 {
		compatible = "arm,pl330\0arm,primecell";
		reg = <0x00 0xff6e0000 0x00 0x4000>;
		interrupts = <0x00 0x07 0x04 0x00 0x00 0x08 0x04 0x00>;
		#dma-cells = <0x01>;
		arm,pl330-periph-burst;
		clocks = <0x09 0xd4>;
		clock-names = "apb_pclk";
		phandle = <0x4d>;
	};

	clock-controller@ff750000 {
		compatible = "rockchip,rk3399-pmucru";
		reg = <0x00 0xff750000 0x00 0x1000>;
		clocks = <0x99>;
		clock-names = "xin24m";
		rockchip,grf = <0x13>;
		#clock-cells = <0x01>;
		#reset-cells = <0x01>;
		assigned-clocks = <0x80 0x01>;
		assigned-clock-rates = <0x284af100>;
		bootph-all;
		phandle = <0x80>;
	};

	clock-controller@ff760000 {
		compatible = "rockchip,rk3399-cru";
		reg = <0x00 0xff760000 0x00 0x1000>;
		clocks = <0x99>;
		clock-names = "xin24m";
		rockchip,grf = <0x21>;
		#clock-cells = <0x01>;
		#reset-cells = <0x01>;
		assigned-clocks = <0x09 0x05 0x09 0x04 0x09 0x06 0x09 0xc0 0x09 0x1c0 0x09 0x140 0x09 0xc2 0x09 0x1c1 0x09 0x142 0x09 0xc9 0x09 0x1c2 0x09 0x143 0x09 0xe3 0x09 0xde 0x09 0x106 0x09 0x178>;
		assigned-clock-rates = <0x2367b880 0x2faf0800 0x3b9aca00 0x8f0d180 0x47868c0 0x23c3460 0x5f5e100 0x5f5e100 0x2faf080 0x23c34600 0x5f5e100 0x2faf080 0x17d78400 0x17d78400 0xbebc200 0xbebc200>;
		bootph-all;
		phandle = <0x09>;
	};

	syscon@ff770000 {
		compatible = "rockchip,rk3399-grf\0syscon\0simple-mfd";
		reg = <0x00 0xff770000 0x00 0x10000>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		bootph-all;
		phandle = <0x21>;

		io-domains {
			compatible = "rockchip,rk3399-io-voltage-domain";
			status = "okay";
			audio-supply = <0x9a>;
			bt656-supply = <0x7f>;
			gpio1830-supply = <0x7f>;
			sdmmc-supply = <0x2c>;
		};

		mipi-dphy-rx0 {
			compatible = "rockchip,rk3399-mipi-dphy-rx0";
			clocks = <0x09 0x77 0x09 0xa5 0x09 0x16f>;
			clock-names = "dphy-ref\0dphy-cfg\0grf";
			power-domains = <0x20 0x0f>;
			#phy-cells = <0x00>;
			status = "disabled";
			phandle = <0xb3>;
		};

		usb2phy@e450 {
			compatible = "rockchip,rk3399-usb2phy";
			reg = <0xe450 0x10>;
			clocks = <0x09 0x7b>;
			clock-names = "phyclk";
			#clock-cells = <0x00>;
			clock-output-names = "clk_usbphy0_480m";
			status = "okay";
			phandle = <0x2f>;

			host-port {
				#phy-cells = <0x00>;
				interrupts = <0x00 0x1b 0x04 0x00>;
				interrupt-names = "linestate";
				status = "okay";
				phy-supply = <0x44>;
				phandle = <0x30>;
			};

			otg-port {
				#phy-cells = <0x00>;
				interrupts = <0x00 0x67 0x04 0x00 0x00 0x68 0x04 0x00 0x00 0x6a 0x04 0x00>;
				interrupt-names = "otg-bvalid\0otg-id\0linestate";
				status = "okay";
				phy-supply = <0x44>;
				phandle = <0x33>;
			};

			port {

				endpoint {
					remote-endpoint = <0x9b>;
					phandle = <0x45>;
				};
			};
		};

		usb2phy@e460 {
			compatible = "rockchip,rk3399-usb2phy";
			reg = <0xe460 0x10>;
			clocks = <0x09 0x7c>;
			clock-names = "phyclk";
			#clock-cells = <0x00>;
			clock-output-names = "clk_usbphy1_480m";
			status = "okay";
			phandle = <0x31>;

			host-port {
				#phy-cells = <0x00>;
				interrupts = <0x00 0x1f 0x04 0x00>;
				interrupt-names = "linestate";
				status = "okay";
				phy-supply = <0x8d>;
				phandle = <0x32>;
			};

			otg-port {
				#phy-cells = <0x00>;
				interrupts = <0x00 0x6c 0x04 0x00 0x00 0x6d 0x04 0x00 0x00 0x6f 0x04 0x00>;
				interrupt-names = "otg-bvalid\0otg-id\0linestate";
				status = "okay";
				phy-supply = <0x8d>;
				phandle = <0x35>;
			};

			port {

				endpoint {
					remote-endpoint = <0x9c>;
					phandle = <0x8e>;
				};
			};
		};

		phy@f780 {
			compatible = "rockchip,rk3399-emmc-phy";
			reg = <0xf780 0x24>;
			clocks = <0x9d>;
			clock-names = "emmcclk";
			drive-impedance-ohm = <0x32>;
			#phy-cells = <0x00>;
			status = "okay";
			rockchip,enable-strobe-pulldown;
			bootph-all;
			phandle = <0x2d>;
		};

		pcie-phy {
			compatible = "rockchip,rk3399-pcie-phy";
			clocks = <0x09 0x8a>;
			clock-names = "refclk";
			#phy-cells = <0x01>;
			resets = <0x09 0x87>;
			reset-names = "phy";
			status = "okay";
			phandle = <0x1a>;
		};
	};

	phy@ff7c0000 {
		compatible = "rockchip,rk3399-typec-phy";
		reg = <0x00 0xff7c0000 0x00 0x40000>;
		clocks = <0x09 0x7e 0x09 0x7d>;
		clock-names = "tcpdcore\0tcpdphy-ref";
		assigned-clocks = <0x09 0x7e>;
		assigned-clock-rates = <0x2faf080>;
		power-domains = <0x20 0x08>;
		resets = <0x09 0x95 0x09 0x94 0x09 0x14c>;
		reset-names = "uphy\0uphy-pipe\0uphy-tcphy";
		rockchip,grf = <0x21>;
		status = "okay";

		dp-port {
			#phy-cells = <0x00>;
			phandle = <0x37>;

			port {

				endpoint {
					remote-endpoint = <0x9e>;
					phandle = <0x47>;
				};
			};
		};

		usb3-port {
			#phy-cells = <0x00>;
			phandle = <0x34>;

			port {

				endpoint {
					remote-endpoint = <0x9f>;
					phandle = <0x46>;
				};
			};
		};
	};

	phy@ff800000 {
		compatible = "rockchip,rk3399-typec-phy";
		reg = <0x00 0xff800000 0x00 0x40000>;
		clocks = <0x09 0x80 0x09 0x7f>;
		clock-names = "tcpdcore\0tcpdphy-ref";
		assigned-clocks = <0x09 0x80>;
		assigned-clock-rates = <0x2faf080>;
		power-domains = <0x20 0x09>;
		resets = <0x09 0x9d 0x09 0x9c 0x09 0x14d>;
		reset-names = "uphy\0uphy-pipe\0uphy-tcphy";
		rockchip,grf = <0x21>;
		status = "okay";

		dp-port {
			#phy-cells = <0x00>;
			phandle = <0x38>;

			port {

				endpoint {
					remote-endpoint = <0xa0>;
					phandle = <0x90>;
				};
			};
		};

		usb3-port {
			#phy-cells = <0x00>;
			phandle = <0x36>;

			port {

				endpoint {
					remote-endpoint = <0xa1>;
					phandle = <0x8f>;
				};
			};
		};
	};

	watchdog@ff848000 {
		compatible = "rockchip,rk3399-wdt\0snps,dw-wdt";
		reg = <0x00 0xff848000 0x00 0x100>;
		clocks = <0x09 0x17c>;
		interrupts = <0x00 0x78 0x04 0x00>;
	};

	rktimer@ff850000 {
		compatible = "rockchip,rk3399-timer";
		reg = <0x00 0xff850000 0x00 0x1000>;
		interrupts = <0x00 0x51 0x04 0x00>;
		clocks = <0x09 0x168 0x09 0x5a>;
		clock-names = "pclk\0timer";
	};

	spdif@ff870000 {
		compatible = "rockchip,rk3399-spdif";
		reg = <0x00 0xff870000 0x00 0x1000>;
		interrupts = <0x00 0x42 0x04 0x00>;
		dmas = <0x5e 0x07>;
		dma-names = "tx";
		clock-names = "mclk\0hclk";
		clocks = <0x09 0x55 0x09 0x1d7>;
		pinctrl-names = "default";
		pinctrl-0 = <0xa2>;
		power-domains = <0x20 0x1c>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	i2s@ff880000 {
		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
		reg = <0x00 0xff880000 0x00 0x1000>;
		rockchip,grf = <0x21>;
		interrupts = <0x00 0x27 0x04 0x00>;
		dmas = <0x5e 0x00 0x5e 0x01>;
		dma-names = "tx\0rx";
		clock-names = "i2s_clk\0i2s_hclk";
		clocks = <0x09 0x56 0x09 0x1d4>;
		pinctrl-names = "bclk_on\0bclk_off";
		pinctrl-0 = <0xa3>;
		pinctrl-1 = <0xa4>;
		power-domains = <0x20 0x1c>;
		#sound-dai-cells = <0x00>;
		status = "okay";
		rockchip,playback-channels = <0x08>;
		rockchip,capture-channels = <0x08>;
	};

	i2s@ff890000 {
		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
		reg = <0x00 0xff890000 0x00 0x1000>;
		interrupts = <0x00 0x28 0x04 0x00>;
		dmas = <0x5e 0x02 0x5e 0x03>;
		dma-names = "tx\0rx";
		clock-names = "i2s_clk\0i2s_hclk";
		clocks = <0x09 0x57 0x09 0x1d5>;
		pinctrl-names = "default";
		pinctrl-0 = <0xa5>;
		power-domains = <0x20 0x1c>;
		#sound-dai-cells = <0x00>;
		status = "okay";
		rockchip,playback-channels = <0x02>;
		rockchip,capture-channels = <0x02>;
	};

	i2s@ff8a0000 {
		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
		reg = <0x00 0xff8a0000 0x00 0x1000>;
		interrupts = <0x00 0x29 0x04 0x00>;
		dmas = <0x5e 0x04 0x5e 0x05>;
		dma-names = "tx\0rx";
		clock-names = "i2s_clk\0i2s_hclk";
		clocks = <0x09 0x58 0x09 0x1d6>;
		power-domains = <0x20 0x1c>;
		#sound-dai-cells = <0x00>;
		status = "okay";
		phandle = <0xb6>;
	};

	vop@ff8f0000 {
		compatible = "rockchip,rk3399-vop-lit";
		reg = <0x00 0xff8f0000 0x00 0x2000 0x00 0xff8f2000 0x00 0x400>;
		interrupts = <0x00 0x77 0x04 0x00>;
		assigned-clocks = <0x09 0xdb 0x09 0x1db>;
		assigned-clock-rates = <0x17d78400 0x5f5e100>;
		clocks = <0x09 0xdb 0x09 0xb5 0x09 0x1db>;
		clock-names = "aclk_vop\0dclk_vop\0hclk_vop";
		iommus = <0xa6>;
		power-domains = <0x20 0x12>;
		resets = <0x09 0x113 0x09 0x117 0x09 0x119>;
		reset-names = "axi\0ahb\0dclk";
		status = "okay";
		bootph-all;

		port {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x11>;

			endpoint@0 {
				reg = <0x00>;
				remote-endpoint = <0xa7>;
				phandle = <0xbf>;
			};

			endpoint@1 {
				reg = <0x01>;
				remote-endpoint = <0xa8>;
				phandle = <0xc4>;
			};

			endpoint@2 {
				reg = <0x02>;
				remote-endpoint = <0xa9>;
				phandle = <0xbd>;
			};

			endpoint@3 {
				reg = <0x03>;
				remote-endpoint = <0xaa>;
				phandle = <0xc1>;
			};

			endpoint@4 {
				reg = <0x04>;
				remote-endpoint = <0xab>;
				phandle = <0x3a>;
			};
		};
	};

	iommu@ff8f3f00 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff8f3f00 0x00 0x100>;
		interrupts = <0x00 0x77 0x04 0x00>;
		interrupt-names = "vopl_mmu";
		clocks = <0x09 0xdb 0x09 0x1db>;
		clock-names = "aclk\0iface";
		power-domains = <0x20 0x12>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0xa6>;
	};

	vop@ff900000 {
		compatible = "rockchip,rk3399-vop-big";
		reg = <0x00 0xff900000 0x00 0x2000 0x00 0xff902000 0x00 0x1000>;
		interrupts = <0x00 0x76 0x04 0x00>;
		assigned-clocks = <0x09 0xd9 0x09 0x1d9>;
		assigned-clock-rates = <0x17d78400 0x5f5e100>;
		clocks = <0x09 0xd9 0x09 0xb4 0x09 0x1d9>;
		clock-names = "aclk_vop\0dclk_vop\0hclk_vop";
		iommus = <0xac>;
		power-domains = <0x20 0x11>;
		resets = <0x09 0x112 0x09 0x116 0x09 0x118>;
		reset-names = "axi\0ahb\0dclk";
		status = "okay";
		bootph-all;

		port {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x12>;

			endpoint@0 {
				reg = <0x00>;
				remote-endpoint = <0xad>;
				phandle = <0xc3>;
			};

			endpoint@1 {
				reg = <0x01>;
				remote-endpoint = <0xae>;
				phandle = <0xbe>;
			};

			endpoint@2 {
				reg = <0x02>;
				remote-endpoint = <0xaf>;
				phandle = <0xbc>;
			};

			endpoint@3 {
				reg = <0x03>;
				remote-endpoint = <0xb0>;
				phandle = <0xc0>;
			};

			endpoint@4 {
				reg = <0x04>;
				remote-endpoint = <0xb1>;
				phandle = <0x39>;
			};
		};
	};

	iommu@ff903f00 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff903f00 0x00 0x100>;
		interrupts = <0x00 0x76 0x04 0x00>;
		interrupt-names = "vopb_mmu";
		clocks = <0x09 0xd9 0x09 0x1d9>;
		clock-names = "aclk\0iface";
		power-domains = <0x20 0x11>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0xac>;
	};

	isp0@ff910000 {
		compatible = "rockchip,rk3399-cif-isp";
		reg = <0x00 0xff910000 0x00 0x4000>;
		interrupts = <0x00 0x2b 0x04 0x00>;
		clocks = <0x09 0x6e 0x09 0xe9 0x09 0x1e3>;
		clock-names = "isp\0aclk\0hclk";
		iommus = <0xb2>;
		phys = <0xb3>;
		phy-names = "dphy";
		power-domains = <0x20 0x13>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
			};
		};
	};

	iommu@ff914000 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff914000 0x00 0x100 0x00 0xff915000 0x00 0x100>;
		interrupts = <0x00 0x2b 0x04 0x00>;
		interrupt-names = "isp0_mmu";
		clocks = <0x09 0xe9 0x09 0x1e3>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		power-domains = <0x20 0x13>;
		rockchip,disable-mmu-reset;
		phandle = <0xb2>;
	};

	isp1@ff920000 {
		compatible = "rockchip,rk3399-cif-isp";
		reg = <0x00 0xff920000 0x00 0x4000>;
		interrupts = <0x00 0x2c 0x04 0x00>;
		clocks = <0x09 0x6f 0x09 0xea 0x09 0x1e4>;
		clock-names = "isp\0aclk\0hclk";
		iommus = <0xb4>;
		phys = <0xb5>;
		phy-names = "dphy";
		power-domains = <0x20 0x14>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
			};
		};
	};

	iommu@ff924000 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff924000 0x00 0x100 0x00 0xff925000 0x00 0x100>;
		interrupts = <0x00 0x2c 0x04 0x00>;
		interrupt-names = "isp1_mmu";
		clocks = <0x09 0xea 0x09 0x1e4>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		power-domains = <0x20 0x14>;
		rockchip,disable-mmu-reset;
		phandle = <0xb4>;
	};

	hdmi-sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,mclk-fs = <0x100>;
		simple-audio-card,name = "hdmi-sound";
		status = "okay";

		simple-audio-card,cpu {
			sound-dai = <0xb6>;
		};

		simple-audio-card,codec {
			sound-dai = <0xb7>;
		};
	};

	hdmi@ff940000 {
		compatible = "rockchip,rk3399-dw-hdmi";
		reg = <0x00 0xff940000 0x00 0x20000>;
		interrupts = <0x00 0x17 0x04 0x00>;
		clocks = <0x09 0x174 0x09 0x71 0x09 0x70 0x09 0x16f 0x09 0x07>;
		clock-names = "iahb\0isfr\0cec\0grf\0ref";
		power-domains = <0x20 0x15>;
		reg-io-width = <0x04>;
		rockchip,grf = <0x21>;
		#sound-dai-cells = <0x00>;
		status = "okay";
		avdd-0v9-supply = <0xb8>;
		avdd-1v8-supply = <0xb9>;
		ddc-i2c-bus = <0xba>;
		pinctrl-names = "default";
		pinctrl-0 = <0xbb>;
		phandle = <0xb7>;

		ports {

			port {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xbc>;
					phandle = <0xaf>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xbd>;
					phandle = <0xa9>;
				};
			};
		};
	};

	dsi@ff960000 {
		compatible = "rockchip,rk3399-mipi-dsi\0snps,dw-mipi-dsi";
		reg = <0x00 0xff960000 0x00 0x8000>;
		interrupts = <0x00 0x2d 0x04 0x00>;
		clocks = <0x09 0xa2 0x09 0x170 0x09 0xa3 0x09 0x16f>;
		clock-names = "ref\0pclk\0phy_cfg\0grf";
		power-domains = <0x20 0x0f>;
		resets = <0x09 0xfb>;
		reset-names = "apb";
		rockchip,grf = <0x21>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xbe>;
					phandle = <0xae>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xbf>;
					phandle = <0xa7>;
				};
			};

			port@1 {
				reg = <0x01>;
			};
		};
	};

	dsi@ff968000 {
		compatible = "rockchip,rk3399-mipi-dsi\0snps,dw-mipi-dsi";
		reg = <0x00 0xff968000 0x00 0x8000>;
		interrupts = <0x00 0x2e 0x04 0x00>;
		clocks = <0x09 0xa2 0x09 0x171 0x09 0xa4 0x09 0x16f>;
		clock-names = "ref\0pclk\0phy_cfg\0grf";
		power-domains = <0x20 0x0f>;
		resets = <0x09 0xfc>;
		reset-names = "apb";
		rockchip,grf = <0x21>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		#phy-cells = <0x00>;
		status = "disabled";
		phandle = <0xb5>;

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xc0>;
					phandle = <0xb0>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xc1>;
					phandle = <0xaa>;
				};
			};

			port@1 {
				reg = <0x01>;
			};
		};
	};

	dp@ff970000 {
		compatible = "rockchip,rk3399-edp";
		reg = <0x00 0xff970000 0x00 0x8000>;
		interrupts = <0x00 0x0a 0x04 0x00>;
		clocks = <0x09 0x16a 0x09 0x16c 0x09 0x16f>;
		clock-names = "dp\0pclk\0grf";
		pinctrl-names = "default";
		pinctrl-0 = <0xc2>;
		power-domains = <0x20 0x19>;
		resets = <0x09 0x11d>;
		reset-names = "dp";
		rockchip,grf = <0x21>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xc3>;
					phandle = <0xad>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xc4>;
					phandle = <0xa8>;
				};
			};

			port@1 {
				reg = <0x01>;
			};
		};
	};

	gpu@ff9a0000 {
		compatible = "rockchip,rk3399-mali\0arm,mali-t860";
		reg = <0x00 0xff9a0000 0x00 0x10000>;
		interrupts = <0x00 0x14 0x04 0x00 0x00 0x15 0x04 0x00 0x00 0x13 0x04 0x00>;
		interrupt-names = "job\0mmu\0gpu";
		clocks = <0x09 0xd0>;
		#cooling-cells = <0x02>;
		power-domains = <0x20 0x23>;
		status = "okay";
		operating-points-v2 = <0xc5>;
		mali-supply = <0xc6>;
		phandle = <0x67>;
	};

	pinctrl {
		compatible = "rockchip,rk3399-pinctrl";
		rockchip,grf = <0x21>;
		rockchip,pmu = <0x13>;
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		bootph-all;

		gpio@ff720000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xff720000 0x00 0x100>;
			clocks = <0x80 0x17>;
			interrupts = <0x00 0x0e 0x04 0x00>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x26>;
		};

		gpio@ff730000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xff730000 0x00 0x100>;
			clocks = <0x80 0x18>;
			interrupts = <0x00 0x0f 0x04 0x00>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x42>;
		};

		gpio@ff780000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xff780000 0x00 0x100>;
			clocks = <0x09 0x150>;
			interrupts = <0x00 0x10 0x04 0x00>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0xd3>;
		};

		gpio@ff788000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xff788000 0x00 0x100>;
			clocks = <0x09 0x151>;
			interrupts = <0x00 0x11 0x04 0x00>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x25>;
		};

		gpio@ff790000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xff790000 0x00 0x100>;
			clocks = <0x09 0x152>;
			interrupts = <0x00 0x12 0x04 0x00>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x1b>;
		};

		pcfg-pull-up {
			bias-pull-up;
			phandle = <0xca>;
		};

		pcfg-pull-down {
			bias-pull-down;
			phandle = <0xcb>;
		};

		pcfg-pull-none {
			bias-disable;
			phandle = <0xc7>;
		};

		pcfg-pull-none-12ma {
			bias-disable;
			drive-strength = <0x0c>;
			phandle = <0xc9>;
		};

		pcfg-pull-none-13ma {
			bias-disable;
			drive-strength = <0x0d>;
			phandle = <0xc8>;
		};

		pcfg-pull-none-18ma {
			bias-disable;
			drive-strength = <0x12>;
		};

		pcfg-pull-none-20ma {
			bias-disable;
			drive-strength = <0x14>;
		};

		pcfg-pull-up-2ma {
			bias-pull-up;
			drive-strength = <0x02>;
		};

		pcfg-pull-up-8ma {
			bias-pull-up;
			drive-strength = <0x08>;
		};

		pcfg-pull-up-18ma {
			bias-pull-up;
			drive-strength = <0x12>;
		};

		pcfg-pull-up-20ma {
			bias-pull-up;
			drive-strength = <0x14>;
		};

		pcfg-pull-down-4ma {
			bias-pull-down;
			drive-strength = <0x04>;
		};

		pcfg-pull-down-8ma {
			bias-pull-down;
			drive-strength = <0x08>;
		};

		pcfg-pull-down-12ma {
			bias-pull-down;
			drive-strength = <0x0c>;
		};

		pcfg-pull-down-18ma {
			bias-pull-down;
			drive-strength = <0x12>;
		};

		pcfg-pull-down-20ma {
			bias-pull-down;
			drive-strength = <0x14>;
		};

		pcfg-output-high {
			output-high;
			phandle = <0xcc>;
		};

		pcfg-output-low {
			output-low;
		};

		pcfg-input-enable {
			input-enable;
		};

		pcfg-input-pull-up {
			input-enable;
			bias-pull-up;
		};

		pcfg-input-pull-down {
			input-enable;
			bias-pull-down;
		};

		clock {

			clk-32k {
				rockchip,pins = <0x00 0x00 0x02 0xc7>;
			};
		};

		cif {

			cif-clkin {
				rockchip,pins = <0x02 0x0a 0x03 0xc7>;
			};

			cif-clkouta {
				rockchip,pins = <0x02 0x0b 0x03 0xc7>;
			};
		};

		edp {

			edp-hpd {
				rockchip,pins = <0x04 0x17 0x02 0xc7>;
				phandle = <0xc2>;
			};
		};

		gmac {

			rgmii-pins {
				rockchip,pins = <0x03 0x11 0x01 0xc8 0x03 0x0e 0x01 0xc7 0x03 0x0d 0x01 0xc7 0x03 0x0c 0x01 0xc8 0x03 0x0b 0x01 0xc7 0x03 0x09 0x01 0xc7 0x03 0x08 0x01 0xc7 0x03 0x07 0x01 0xc7 0x03 0x06 0x01 0xc7 0x03 0x05 0x01 0xc8 0x03 0x04 0x01 0xc8 0x03 0x03 0x01 0xc7 0x03 0x02 0x01 0xc7 0x03 0x01 0x01 0xc8 0x03 0x00 0x01 0xc8>;
				phandle = <0x24>;
			};

			rmii-pins {
				rockchip,pins = <0x03 0x0d 0x01 0xc7 0x03 0x0c 0x01 0xc8 0x03 0x0b 0x01 0xc7 0x03 0x0a 0x01 0xc7 0x03 0x09 0x01 0xc7 0x03 0x08 0x01 0xc7 0x03 0x07 0x01 0xc7 0x03 0x06 0x01 0xc7 0x03 0x05 0x01 0xc8 0x03 0x04 0x01 0xc8>;
			};
		};

		i2c0 {

			i2c0-xfer {
				rockchip,pins = <0x01 0x0f 0x02 0xc7 0x01 0x10 0x02 0xc7>;
				phandle = <0x86>;
			};
		};

		i2c1 {

			i2c1-xfer {
				rockchip,pins = <0x04 0x02 0x01 0xc7 0x04 0x01 0x01 0xc7>;
				phandle = <0x3c>;
			};
		};

		i2c2 {

			i2c2-xfer {
				rockchip,pins = <0x02 0x01 0x02 0xc9 0x02 0x00 0x02 0xc9>;
				phandle = <0x3d>;
			};
		};

		i2c3 {

			i2c3-xfer {
				rockchip,pins = <0x04 0x11 0x01 0xc7 0x04 0x10 0x01 0xc7>;
				phandle = <0x3e>;
			};
		};

		i2c4 {

			i2c4-xfer {
				rockchip,pins = <0x01 0x0c 0x01 0xc7 0x01 0x0b 0x01 0xc7>;
				phandle = <0x8b>;
			};
		};

		i2c5 {

			i2c5-xfer {
				rockchip,pins = <0x03 0x0b 0x02 0xc7 0x03 0x0a 0x02 0xc7>;
				phandle = <0x3f>;
			};
		};

		i2c6 {

			i2c6-xfer {
				rockchip,pins = <0x02 0x0a 0x02 0xc7 0x02 0x09 0x02 0xc7>;
				phandle = <0x40>;
			};
		};

		i2c7 {

			i2c7-xfer {
				rockchip,pins = <0x02 0x08 0x02 0xc7 0x02 0x07 0x02 0xc7>;
				phandle = <0x41>;
			};
		};

		i2c8 {

			i2c8-xfer {
				rockchip,pins = <0x01 0x15 0x01 0xc7 0x01 0x14 0x01 0xc7>;
				phandle = <0x91>;
			};
		};

		i2s0 {

			i2s0-2ch-bus {
				rockchip,pins = <0x03 0x18 0x01 0xc7 0x03 0x19 0x01 0xc7 0x03 0x1a 0x01 0xc7 0x03 0x1b 0x01 0xc7 0x03 0x1f 0x01 0xc7 0x04 0x00 0x01 0xc7>;
			};

			i2s0-8ch-bus {
				rockchip,pins = <0x03 0x18 0x01 0xc7 0x03 0x19 0x01 0xc7 0x03 0x1a 0x01 0xc7 0x03 0x1b 0x01 0xc7 0x03 0x1c 0x01 0xc7 0x03 0x1d 0x01 0xc7 0x03 0x1e 0x01 0xc7 0x03 0x1f 0x01 0xc7 0x04 0x00 0x01 0xc7>;
				phandle = <0xa3>;
			};

			i2s0-8ch-bus-bclk-off {
				rockchip,pins = <0x03 0x18 0x00 0xc7 0x03 0x19 0x01 0xc7 0x03 0x1a 0x01 0xc7 0x03 0x1b 0x01 0xc7 0x03 0x1c 0x01 0xc7 0x03 0x1d 0x01 0xc7 0x03 0x1e 0x01 0xc7 0x03 0x1f 0x01 0xc7 0x04 0x00 0x01 0xc7>;
				phandle = <0xa4>;
			};
		};

		i2s1 {

			i2s1-2ch-bus {
				rockchip,pins = <0x04 0x03 0x01 0xc7 0x04 0x04 0x01 0xc7 0x04 0x05 0x01 0xc7 0x04 0x06 0x01 0xc7 0x04 0x07 0x01 0xc7>;
				phandle = <0xa5>;
			};

			i2s1-2ch-bus-bclk-off {
				rockchip,pins = <0x04 0x03 0x00 0xc7 0x04 0x04 0x01 0xc7 0x04 0x05 0x01 0xc7 0x04 0x06 0x01 0xc7 0x04 0x07 0x01 0xc7>;
			};
		};

		sdio0 {

			sdio0-bus1 {
				rockchip,pins = <0x02 0x14 0x01 0xca>;
			};

			sdio0-bus4 {
				rockchip,pins = <0x02 0x14 0x01 0xca 0x02 0x15 0x01 0xca 0x02 0x16 0x01 0xca 0x02 0x17 0x01 0xca>;
			};

			sdio0-cmd {
				rockchip,pins = <0x02 0x18 0x01 0xca>;
			};

			sdio0-clk {
				rockchip,pins = <0x02 0x19 0x01 0xc7>;
			};

			sdio0-cd {
				rockchip,pins = <0x02 0x1a 0x01 0xca>;
			};

			sdio0-pwr {
				rockchip,pins = <0x02 0x1b 0x01 0xca>;
			};

			sdio0-bkpwr {
				rockchip,pins = <0x02 0x1c 0x01 0xca>;
			};

			sdio0-wp {
				rockchip,pins = <0x00 0x03 0x01 0xca>;
			};

			sdio0-int {
				rockchip,pins = <0x00 0x04 0x01 0xca>;
			};
		};

		sdmmc {

			sdmmc-bus1 {
				rockchip,pins = <0x04 0x08 0x01 0xca>;
			};

			sdmmc-bus4 {
				rockchip,pins = <0x04 0x08 0x01 0xca 0x04 0x09 0x01 0xca 0x04 0x0a 0x01 0xca 0x04 0x0b 0x01 0xca>;
				phandle = <0x2a>;
			};

			sdmmc-clk {
				rockchip,pins = <0x04 0x0c 0x01 0xc7>;
				phandle = <0x27>;
			};

			sdmmc-cmd {
				rockchip,pins = <0x04 0x0d 0x01 0xca>;
				phandle = <0x28>;
			};

			sdmmc-cd {
				rockchip,pins = <0x00 0x07 0x01 0xca>;
				phandle = <0x29>;
			};

			sdmmc-wp {
				rockchip,pins = <0x00 0x08 0x01 0xca>;
			};

			vcc3v0-sd-en {
				rockchip,pins = <0x04 0x1e 0x00 0xc7>;
				phandle = <0xd6>;
			};
		};

		suspend {

			ap-pwroff {
				rockchip,pins = <0x01 0x05 0x01 0xc7>;
			};

			ddrio-pwroff {
				rockchip,pins = <0x00 0x01 0x01 0xc7>;
			};
		};

		spdif {

			spdif-bus {
				rockchip,pins = <0x04 0x15 0x01 0xc7>;
				phandle = <0xa2>;
			};

			spdif-bus-1 {
				rockchip,pins = <0x03 0x10 0x03 0xc7>;
			};
		};

		spi0 {

			spi0-clk {
				rockchip,pins = <0x03 0x06 0x02 0xca>;
				phandle = <0x4e>;
			};

			spi0-cs0 {
				rockchip,pins = <0x03 0x07 0x02 0xca>;
				phandle = <0x51>;
			};

			spi0-cs1 {
				rockchip,pins = <0x03 0x08 0x02 0xca>;
			};

			spi0-tx {
				rockchip,pins = <0x03 0x05 0x02 0xca>;
				phandle = <0x4f>;
			};

			spi0-rx {
				rockchip,pins = <0x03 0x04 0x02 0xca>;
				phandle = <0x50>;
			};
		};

		spi1 {

			spi1-clk {
				rockchip,pins = <0x01 0x09 0x02 0xca>;
				phandle = <0x52>;
			};

			spi1-cs0 {
				rockchip,pins = <0x01 0x0a 0x02 0xca>;
				phandle = <0x55>;
			};

			spi1-rx {
				rockchip,pins = <0x01 0x07 0x02 0xca>;
				phandle = <0x54>;
			};

			spi1-tx {
				rockchip,pins = <0x01 0x08 0x02 0xca>;
				phandle = <0x53>;
			};
		};

		spi2 {

			spi2-clk {
				rockchip,pins = <0x02 0x0b 0x01 0xca>;
				phandle = <0x56>;
			};

			spi2-cs0 {
				rockchip,pins = <0x02 0x0c 0x01 0xca>;
				phandle = <0x59>;
			};

			spi2-rx {
				rockchip,pins = <0x02 0x09 0x01 0xca>;
				phandle = <0x58>;
			};

			spi2-tx {
				rockchip,pins = <0x02 0x0a 0x01 0xca>;
				phandle = <0x57>;
			};
		};

		spi3 {

			spi3-clk {
				rockchip,pins = <0x01 0x11 0x01 0xca>;
				phandle = <0x81>;
			};

			spi3-cs0 {
				rockchip,pins = <0x01 0x12 0x01 0xca>;
				phandle = <0x84>;
			};

			spi3-rx {
				rockchip,pins = <0x01 0x0f 0x01 0xca>;
				phandle = <0x83>;
			};

			spi3-tx {
				rockchip,pins = <0x01 0x10 0x01 0xca>;
				phandle = <0x82>;
			};
		};

		spi4 {

			spi4-clk {
				rockchip,pins = <0x03 0x02 0x02 0xca>;
				phandle = <0x5a>;
			};

			spi4-cs0 {
				rockchip,pins = <0x03 0x03 0x02 0xca>;
				phandle = <0x5d>;
			};

			spi4-rx {
				rockchip,pins = <0x03 0x00 0x02 0xca>;
				phandle = <0x5c>;
			};

			spi4-tx {
				rockchip,pins = <0x03 0x01 0x02 0xca>;
				phandle = <0x5b>;
			};
		};

		spi5 {

			spi5-clk {
				rockchip,pins = <0x02 0x16 0x02 0xca>;
				phandle = <0x5f>;
			};

			spi5-cs0 {
				rockchip,pins = <0x02 0x17 0x02 0xca>;
				phandle = <0x62>;
			};

			spi5-rx {
				rockchip,pins = <0x02 0x14 0x02 0xca>;
				phandle = <0x61>;
			};

			spi5-tx {
				rockchip,pins = <0x02 0x15 0x02 0xca>;
				phandle = <0x60>;
			};
		};

		testclk {

			test-clkout0 {
				rockchip,pins = <0x00 0x00 0x01 0xc7>;
			};

			test-clkout1 {
				rockchip,pins = <0x02 0x19 0x02 0xc7>;
			};

			test-clkout2 {
				rockchip,pins = <0x00 0x08 0x03 0xc7>;
			};
		};

		tsadc {

			otp-pin {
				rockchip,pins = <0x01 0x06 0x00 0xc7>;
				phandle = <0x68>;
			};

			otp-out {
				rockchip,pins = <0x01 0x06 0x01 0xc7>;
				phandle = <0x69>;
			};
		};

		uart0 {

			uart0-xfer {
				rockchip,pins = <0x02 0x10 0x01 0xca 0x02 0x11 0x01 0xc7>;
				phandle = <0x48>;
			};

			uart0-cts {
				rockchip,pins = <0x02 0x12 0x01 0xc7>;
				phandle = <0x49>;
			};

			uart0-rts {
				rockchip,pins = <0x02 0x13 0x01 0xc7>;
			};
		};

		uart1 {

			uart1-xfer {
				rockchip,pins = <0x03 0x0c 0x02 0xca 0x03 0x0d 0x02 0xc7>;
				phandle = <0x4a>;
			};
		};

		uart2a {

			uart2a-xfer {
				rockchip,pins = <0x04 0x08 0x02 0xca 0x04 0x09 0x02 0xc7>;
			};
		};

		uart2b {

			uart2b-xfer {
				rockchip,pins = <0x04 0x10 0x02 0xca 0x04 0x11 0x02 0xc7>;
			};
		};

		uart2c {

			uart2c-xfer {
				rockchip,pins = <0x04 0x13 0x01 0xca 0x04 0x14 0x01 0xc7>;
				phandle = <0x4b>;
			};
		};

		uart3 {

			uart3-xfer {
				rockchip,pins = <0x03 0x0e 0x02 0xca 0x03 0x0f 0x02 0xc7>;
				phandle = <0x4c>;
			};

			uart3-cts {
				rockchip,pins = <0x03 0x10 0x02 0xc7>;
			};

			uart3-rts {
				rockchip,pins = <0x03 0x11 0x02 0xc7>;
			};
		};

		uart4 {

			uart4-xfer {
				rockchip,pins = <0x01 0x07 0x01 0xca 0x01 0x08 0x01 0xc7>;
				phandle = <0x85>;
			};
		};

		uarthdcp {

			uarthdcp-xfer {
				rockchip,pins = <0x04 0x15 0x02 0xca 0x04 0x16 0x02 0xc7>;
			};
		};

		pwm0 {

			pwm0-pin {
				rockchip,pins = <0x04 0x12 0x01 0xc7>;
				phandle = <0x92>;
			};

			pwm0-pin-pull-down {
				rockchip,pins = <0x04 0x12 0x01 0xcb>;
			};

			vop0-pwm-pin {
				rockchip,pins = <0x04 0x12 0x02 0xc7>;
			};

			vop1-pwm-pin {
				rockchip,pins = <0x04 0x12 0x03 0xc7>;
			};
		};

		pwm1 {

			pwm1-pin {
				rockchip,pins = <0x04 0x16 0x01 0xc7>;
				phandle = <0x93>;
			};

			pwm1-pin-pull-down {
				rockchip,pins = <0x04 0x16 0x01 0xcb>;
			};
		};

		pwm2 {

			pwm2-pin {
				rockchip,pins = <0x01 0x13 0x01 0xc7>;
				phandle = <0x94>;
			};

			pwm2-pin-pull-down {
				rockchip,pins = <0x01 0x13 0x01 0xcb>;
			};
		};

		pwm3a {

			pwm3a-pin {
				rockchip,pins = <0x00 0x06 0x01 0xc7>;
				phandle = <0x95>;
			};
		};

		pwm3b {

			pwm3b-pin {
				rockchip,pins = <0x01 0x0e 0x01 0xc7>;
			};
		};

		hdmi {

			hdmi-i2c-xfer {
				rockchip,pins = <0x04 0x11 0x03 0xc7 0x04 0x10 0x03 0xc7>;
			};

			hdmi-cec {
				rockchip,pins = <0x04 0x17 0x01 0xc7>;
				phandle = <0xbb>;
			};
		};

		pcie {

			pci-clkreqn-cpm {
				rockchip,pins = <0x02 0x1a 0x00 0xc7>;
			};

			pci-clkreqnb-cpm {
				rockchip,pins = <0x04 0x18 0x00 0xc7>;
			};

			vcc3v3-pcie-en {
				rockchip,pins = <0x01 0x11 0x00 0xc7>;
				phandle = <0xd7>;
			};

			pcie-perst {
				rockchip,pins = <0x04 0x19 0x00 0xc7>;
				phandle = <0x1c>;
			};
		};

		buttons {

			pwr-key-l {
				rockchip,pins = <0x00 0x05 0x00 0xca>;
				phandle = <0xce>;
			};
		};

		ir {

			ir-int {
				rockchip,pins = <0x00 0x06 0x00 0xc7>;
				phandle = <0xcf>;
			};
		};

		lcd-panel {

			lcd-panel-reset {
				rockchip,pins = <0x04 0x1d 0x00 0xca>;
			};
		};

		leds {

			led-red-pin {
				rockchip,pins = <0x00 0x0d 0x00 0xc7>;
				phandle = <0xd1>;
			};

			led-green-pin {
				rockchip,pins = <0x02 0x1b 0x00 0xc7>;
				phandle = <0xd0>;
			};

			led-yellow-pin {
				rockchip,pins = <0x00 0x02 0x00 0xc7>;
				phandle = <0xd2>;
			};
		};

		ngff {

			vcc3v3-ngff-en {
				rockchip,pins = <0x04 0x1b 0x00 0xc7>;
				phandle = <0xd9>;
			};
		};

		pmic {

			vsel1-pin {
				rockchip,pins = <0x01 0x12 0x00 0xcb>;
				phandle = <0x89>;
			};

			vsel2-pin {
				rockchip,pins = <0x01 0x0e 0x00 0xcb>;
				phandle = <0x8a>;
			};

			pmic-int-l {
				rockchip,pins = <0x01 0x15 0x00 0xca>;
				phandle = <0x87>;
			};
		};

		sdio-pwrseq {

			wifi-enable-h {
				rockchip,pins = <0x00 0x0a 0x00 0xc7>;
				phandle = <0xd5>;
			};
		};

		usb2 {

			vcc5v0-host-en {
				rockchip,pins = <0x01 0x00 0x00 0xc7>;
				phandle = <0xda>;
			};

			vcc-sys-en {
				rockchip,pins = <0x02 0x06 0x00 0xc7>;
				phandle = <0xde>;
			};

			hub-rst {
				rockchip,pins = <0x02 0x04 0x00 0xcc>;
				phandle = <0xdd>;
			};
		};

		usb-typec {

			vcc-vbus-typec1-en {
				rockchip,pins = <0x01 0x0d 0x00 0xc7>;
				phandle = <0xdc>;
			};
		};

		fusb30x {

			fusb0-int {
				rockchip,pins = <0x01 0x02 0x00 0xca>;
				phandle = <0x43>;
			};

			fusb1-int {
				rockchip,pins = <0x01 0x01 0x00 0xca>;
				phandle = <0x8c>;
			};
		};
	};

	opp-table-0 {
		compatible = "operating-points-v2";
		opp-shared;
		phandle = <0x0c>;

		opp00 {
			opp-hz = <0x00 0x18519600>;
			opp-microvolt = "\0\f5";
			clock-latency-ns = <0x9c40>;
		};

		opp01 {
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xc96a8>;
		};

		opp02 {
			opp-hz = <0x00 0x30a32c00>;
			opp-microvolt = <0xcf850>;
		};

		opp03 {
			opp-hz = <0x00 0x3c14dc00>;
			opp-microvolt = <0xdbba0>;
		};

		opp04 {
			opp-hz = <0x00 0x47868c00>;
			opp-microvolt = <0xee098>;
		};

		opp05 {
			opp-hz = <0x00 0x54667200>;
			opp-microvolt = <0x10c8e0>;
		};

		opp06 {
			opp-hz = <0x00 0x5a1f4a00>;
			opp-microvolt = <0x118c30>;
		};
	};

	opp-table-1 {
		compatible = "operating-points-v2";
		opp-shared;
		phandle = <0x0f>;

		opp00 {
			opp-hz = <0x00 0x18519600>;
			opp-microvolt = "\0\f5";
			clock-latency-ns = <0x9c40>;
		};

		opp01 {
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = "\0\f5";
		};

		opp02 {
			opp-hz = <0x00 0x30a32c00>;
			opp-microvolt = <0xc96a8>;
		};

		opp03 {
			opp-hz = <0x00 0x3c14dc00>;
			opp-microvolt = <0xcf850>;
		};

		opp04 {
			opp-hz = <0x00 0x47868c00>;
			opp-microvolt = <0xdbba0>;
		};

		opp05 {
			opp-hz = <0x00 0x54667200>;
			opp-microvolt = <0xee098>;
		};

		opp06 {
			opp-hz = <0x00 0x5fd82200>;
			opp-microvolt = <0x100590>;
		};

		opp07 {
			opp-hz = <0x00 0x6b49d200>;
			opp-microvolt = <0x118c30>;
		};

		opp08 {
			opp-hz = <0x00 0x7829b800>;
			opp-microvolt = <0x1312d0>;
		};
	};

	opp-table-2 {
		compatible = "operating-points-v2";
		phandle = <0xc5>;

		opp00 {
			opp-hz = <0x00 0xbebc200>;
			opp-microvolt = "\0\f5";
		};

		opp01 {
			opp-hz = <0x00 0x11b3dc40>;
			opp-microvolt = "\0\f5";
		};

		opp02 {
			opp-hz = <0x00 0x17d78400>;
			opp-microvolt = <0xc96a8>;
		};

		opp03 {
			opp-hz = <0x00 0x1dcd6500>;
			opp-microvolt = <0xcf850>;
		};

		opp04 {
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xe1d48>;
		};

		opp05 {
			opp-hz = <0x00 0x2faf0800>;
			opp-microvolt = <0x106738>;
		};
	};

	opp-table-3 {
		compatible = "operating-points-v2";
		phandle = <0x15>;

		opp00 {
			opp-hz = <0x00 0x17d78400>;
			opp-microvolt = <0xdbba0>;
		};

		opp01 {
			opp-hz = <0x00 0x27b25a80>;
			opp-microvolt = <0xdbba0>;
		};

		opp02 {
			opp-hz = <0x00 0x2faf0800>;
			opp-microvolt = <0xdbba0>;
		};

		opp03 {
			opp-hz = <0x00 0x37502800>;
			opp-microvolt = <0xe1d48>;
		};
	};

	chosen {
		stdout-path = "serial2:1500000n8";
		u-boot,spl-boot-order = "same-as-spl\0/spi@ff1d0000/flash@0\0/mmc@fe330000\0/mmc@fe320000";
	};

	external-gmac-clock {
		compatible = "fixed-clock";
		clock-frequency = <0x7735940>;
		clock-output-names = "clkin_gmac";
		#clock-cells = <0x00>;
		phandle = <0x22>;
	};

	adc-keys {
		compatible = "adc-keys";
		io-channels = <0xcd 0x01>;
		io-channel-names = "buttons";
		keyup-threshold-microvolt = <0x16e360>;
		poll-interval = <0x64>;

		button-recovery {
			label = "Recovery";
			linux,code = <0x168>;
			press-threshold-microvolt = <0x4650>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		pinctrl-names = "default";
		pinctrl-0 = <0xce>;

		key-power {
			debounce-interval = <0x64>;
			gpios = <0x26 0x05 0x01>;
			label = "GPIO Key Power";
			linux,code = <0x74>;
			wakeup-source;
		};
	};

	ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <0x26 0x06 0x01>;
		pinctrl-names = "default";
		pinctrl-0 = <0xcf>;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <0xd0 0xd1 0xd2>;

		led-green {
			label = "green";
			color = <0x02>;
			function = "status";
			gpios = <0xd3 0x1b 0x00>;
			default-state = "on";
			panic-indicator;
		};

		led-red {
			label = "red";
			color = <0x01>;
			function = "power";
			gpios = <0x26 0x0d 0x00>;
			default-state = "on";
		};

		led-yellow {
			label = "yellow";
			color = <0x06>;
			function = "activity";
			gpios = <0x26 0x02 0x00>;
			default-state = "off";
			linux,default-trigger = "activity";
		};
	};

	sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <0xd4 0x01>;
		clock-names = "ext_clock";
		pinctrl-names = "default";
		pinctrl-0 = <0xd5>;
		reset-gpios = <0x26 0x0a 0x01>;
	};

	vcc-vbus-typec0 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_vbus_typec0";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		phandle = <0x44>;
	};

	sys-12v {
		compatible = "regulator-fixed";
		regulator-name = "sys_12v";
		regulator-min-microvolt = <0xb71b00>;
		regulator-max-microvolt = <0xb71b00>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0xd8>;
	};

	vcc1v8-s3 {
		compatible = "regulator-fixed";
		regulator-name = "vcc1v8_s3";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x1b7740>;
		regulator-max-microvolt = <0x1b7740>;
		vin-supply = <0x2e>;
		phandle = <0x3b>;
	};

	vcc3v0-sd {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0x1b 0x1e 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xd6>;
		regulator-name = "vcc3v0_sd";
		regulator-boot-on;
		regulator-min-microvolt = <0x2dc6c0>;
		regulator-max-microvolt = <0x2dc6c0>;
		vin-supply = <0x88>;
		phandle = <0x2b>;
	};

	vcc3v3-pcie {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_pcie";
		enable-active-high;
		gpio = <0x42 0x11 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xd7>;
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		vin-supply = <0xd8>;
		phandle = <0x1d>;
	};

	vcca-0v9 {
		compatible = "regulator-fixed";
		regulator-name = "vcca_0v9";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0xdbba0>;
		regulator-max-microvolt = <0xdbba0>;
		vin-supply = <0x88>;
		phandle = <0x1f>;
	};

	vcc3v3-sys {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		vin-supply = <0xd8>;
		phandle = <0x88>;
	};

	vcc3v3-ngff {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_ngff";
		enable-active-high;
		gpio = <0x1b 0x1b 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xd9>;
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		vin-supply = <0xd8>;
	};

	vcc5v0-host-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0x42 0x00 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xda>;
		regulator-name = "vcc5v0_host";
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <0xdb>;
	};

	vcc-vbus-typec1 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0x42 0x0d 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xdc>;
		regulator-name = "vcc_vbus_typec1";
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <0xdb>;
		phandle = <0x8d>;

		regulator-state-mem {
			regulator-off-in-suspend;
		};
	};

	vcc_hub_en-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0xd3 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xdd>;
		regulator-name = "vcc_hub_en";
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <0xdb>;
	};

	vcc-sys {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0xd3 0x06 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xde>;
		regulator-name = "vcc_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		vin-supply = <0xd8>;
		phandle = <0xdb>;
	};

	vdd-log {
		compatible = "pwm-regulator";
		pwms = <0xdf 0x00 0x61a8 0x01>;
		regulator-name = "vdd_log";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x6ddd0>;
		regulator-max-microvolt = <0x155cc0>;
		pwm-supply = <0x88>;
		regulator-init-microvolt = <0xe7ef0>;
	};

	binman {
		multiple-images;

		simple-bin {
			filename = "u-boot-rockchip.bin";
			pad-byte = <0xff>;

			mkimage {
				filename = "idbloader.img";
				args = "-n\0rk3399\0-T\0rksd";
				multiple-data-files;

				u-boot-tpl {
				};

				u-boot-spl {
				};
			};

			fit {
				description = "FIT image for U-Boot with bl31 (TF-A)";
				#address-cells = <0x01>;
				fit,fdt-list = "of-list";
				filename = "u-boot.itb";
				fit,external-offset = <0x00>;
				fit,align = <0x200>;
				offset = <0x31000>;

				images {

					u-boot {
						description = "U-Boot (64-bit)";
						type = "standalone";
						os = "U-Boot";
						arch = "arm64";
						load = <0x200000>;
						entry = <0x200000>;
						compression = "lzma";

						u-boot-nodtb {
							compress = "lzma";
						};
					};

					@atf-SEQ {
						fit,operation = "split-elf";
						description = "ARM Trusted Firmware";
						type = "firmware";
						arch = "arm64";
						os = "arm-trusted-firmware";
						compression = "none";
						fit,load;
						fit,entry;
						fit,data;

						atf-bl31 {
						};
					};

					@tee-SEQ {
						fit,operation = "split-elf";
						description = "TEE";
						type = "tee";
						arch = "arm64";
						os = "tee";
						compression = "none";
						fit,load;
						fit,entry;
						fit,data;

						tee-os {
							optional;
						};
					};

					@fdt-SEQ {
						description = "fdt-NAME";
						compression = "none";
						type = "flat_dt";
					};
				};

				configurations {
					default = "@config-DEFAULT-SEQ";

					@config-SEQ {
						description = "NAME.dtb";
						fdt = "fdt-SEQ";
						fit,firmware = "atf-1\0u-boot";
						fit,loadables;
					};
				};
			};
		};

		simple-bin-spi {
			filename = "u-boot-rockchip-spi.bin";
			pad-byte = <0xff>;

			mkimage {
				filename = "idbloader-spi.img";
				args = "-n\0rk3399\0-T\0rkspi";
				multiple-data-files;

				u-boot-tpl {
				};

				u-boot-spl {
				};
			};

			fit {
				type = "blob";
				filename = "u-boot.itb";
				offset = <0x62000>;
			};
		};
	};

	syscon@ff620000 {
		bootph-all;
		compatible = "rockchip,rk3399-cic\0syscon";
		reg = <0x00 0xff620000 0x00 0x100>;
	};

	syscon@ff330000 {
		bootph-all;
		compatible = "rockchip,rk3399-pmusgrf\0syscon";
		reg = <0x00 0xff330000 0x00 0xe3d4>;
	};

	config {
		u-boot,spl-payload-offset = <0x62000>;
	};

	smbios {
		compatible = "u-boot,sysinfo-smbios";

		smbios {

			system {
				manufacturer = "libre-computer";
				product = "roc-rk3399-pc";
			};

			baseboard {
				manufacturer = "libre-computer";
				product = "roc-rk3399-pc";
			};

			chassis {
				manufacturer = "libre-computer";
				product = "roc-rk3399-pc";
			};
		};
	};
};