/dts-v1/;

/ {
	compatible = "firefly,roc-rk3399-pc\0rockchip,rk3399";
	interrupt-parent = <0x01>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	model = "Firefly ROC-RK3399-PC Board";

	aliases {
		ethernet0 = "/ethernet@fe300000";
		i2c0 = "/i2c@ff3c0000";
		i2c1 = "/i2c@ff110000";
		i2c2 = "/i2c@ff120000";
		i2c3 = "/i2c@ff130000";
		i2c4 = "/i2c@ff3d0000";
		i2c5 = "/i2c@ff140000";
		i2c6 = "/i2c@ff150000";
		i2c7 = "/i2c@ff160000";
		i2c8 = "/i2c@ff3e0000";
		serial0 = "/serial@ff180000";
		serial1 = "/serial@ff190000";
		serial2 = "/serial@ff1a0000";
		serial3 = "/serial@ff1b0000";
		serial4 = "/serial@ff370000";
		mmc0 = "/mmc@fe330000";
		mmc1 = "/mmc@fe320000";
		pci0 = "/pcie@f8000000";
		spi1 = "/spi@ff1d0000";
	};

	cpus {
		#address-cells = <0x02>;
		#size-cells = <0x00>;

		cpu-map {

			cluster0 {

				core0 {
					cpu = <0x02>;
				};

				core1 {
					cpu = <0x03>;
				};

				core2 {
					cpu = <0x04>;
				};

				core3 {
					cpu = <0x05>;
				};
			};

			cluster1 {

				core0 {
					cpu = <0x06>;
				};

				core1 {
					cpu = <0x07>;
				};
			};
		};

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x00 0x00>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x1e5>;
			clocks = <0x08 0x08>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x64>;
			cpu-idle-states = <0x09 0x0a>;
			operating-points-v2 = <0x0b>;
			cpu-supply = <0x0c>;
			phandle = <0x02>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x00 0x01>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x1e5>;
			clocks = <0x08 0x08>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x64>;
			cpu-idle-states = <0x09 0x0a>;
			operating-points-v2 = <0x0b>;
			cpu-supply = <0x0c>;
			phandle = <0x03>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x00 0x02>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x1e5>;
			clocks = <0x08 0x08>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x64>;
			cpu-idle-states = <0x09 0x0a>;
			operating-points-v2 = <0x0b>;
			cpu-supply = <0x0c>;
			phandle = <0x04>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x00 0x03>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x1e5>;
			clocks = <0x08 0x08>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x64>;
			cpu-idle-states = <0x09 0x0a>;
			operating-points-v2 = <0x0b>;
			cpu-supply = <0x0c>;
			phandle = <0x05>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x00 0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x400>;
			clocks = <0x08 0x09>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x1b4>;
			cpu-idle-states = <0x09 0x0a>;
			operating-points-v2 = <0x0d>;
			cpu-supply = <0x0e>;
			phandle = <0x06>;
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x00 0x101>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x400>;
			clocks = <0x08 0x09>;
			#cooling-cells = <0x02>;
			dynamic-power-coefficient = <0x1b4>;
			cpu-idle-states = <0x09 0x0a>;
			operating-points-v2 = <0x0d>;
			cpu-supply = <0x0e>;
			phandle = <0x07>;
		};

		idle-states {
			entry-method = "psci";

			cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x10000>;
				entry-latency-us = <0x78>;
				exit-latency-us = <0xfa>;
				min-residency-us = <0x384>;
				phandle = <0x09>;
			};

			cluster-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <0x190>;
				exit-latency-us = <0x1f4>;
				min-residency-us = <0x7d0>;
				phandle = <0x0a>;
			};
		};
	};

	display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <0x0f 0x10>;
	};

	pmu_a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <0x01 0x07 0x08 0x11>;
	};

	pmu_a72 {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <0x01 0x07 0x08 0x12>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <0x01 0x0d 0x08 0x00 0x01 0x0e 0x08 0x00 0x01 0x0b 0x08 0x00 0x01 0x0a 0x08 0x00>;
		arm,no-tick-in-suspend;
	};

	xin24m {
		compatible = "fixed-clock";
		clock-frequency = <0x16e3600>;
		clock-output-names = "xin24m";
		#clock-cells = <0x00>;
	};

	pcie@f8000000 {
		compatible = "rockchip,rk3399-pcie";
		reg = <0x00 0xf8000000 0x00 0x2000000 0x00 0xfd000000 0x00 0x1000000>;
		reg-names = "axi-base\0apb-base";
		device_type = "pci";
		#address-cells = <0x03>;
		#size-cells = <0x02>;
		#interrupt-cells = <0x01>;
		aspm-no-l0s;
		bus-range = <0x00 0x1f>;
		clocks = <0x08 0xc5 0x08 0xc4 0x08 0x147 0x08 0xa0>;
		clock-names = "aclk\0aclk-perf\0hclk\0pm";
		interrupts = <0x00 0x31 0x04 0x00 0x00 0x32 0x04 0x00 0x00 0x33 0x04 0x00>;
		interrupt-names = "sys\0legacy\0client";
		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
		interrupt-map = <0x00 0x00 0x00 0x01 0x13 0x00 0x00 0x00 0x00 0x02 0x13 0x01 0x00 0x00 0x00 0x03 0x13 0x02 0x00 0x00 0x00 0x04 0x13 0x03>;
		max-link-speed = <0x01>;
		msi-map = <0x00 0x14 0x00 0x1000>;
		phys = <0x15 0x00 0x15 0x01 0x15 0x02 0x15 0x03>;
		phy-names = "pcie-phy-0\0pcie-phy-1\0pcie-phy-2\0pcie-phy-3";
		ranges = <0x82000000 0x00 0xfa000000 0x00 0xfa000000 0x00 0x1e00000 0x81000000 0x00 0xfbe00000 0x00 0xfbe00000 0x00 0x100000>;
		resets = <0x08 0x82 0x08 0x83 0x08 0x84 0x08 0x85 0x08 0x86 0x08 0x81 0x08 0x80>;
		reset-names = "core\0mgmt\0mgmt-sticky\0pipe\0pm\0pclk\0aclk";
		status = "disabled";

		interrupt-controller {
			interrupt-controller;
			#address-cells = <0x00>;
			#interrupt-cells = <0x01>;
			phandle = <0x13>;
		};
	};

	ethernet@fe300000 {
		compatible = "rockchip,rk3399-gmac";
		reg = <0x00 0xfe300000 0x00 0x10000>;
		interrupts = <0x00 0x0c 0x04 0x00>;
		interrupt-names = "macirq";
		clocks = <0x08 0x69 0x08 0x67 0x08 0x68 0x08 0x66 0x08 0x6a 0x08 0xd5 0x08 0x166>;
		clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_ref\0clk_mac_refout\0aclk_mac\0pclk_mac";
		power-domains = <0x16 0x16>;
		resets = <0x08 0x89>;
		reset-names = "stmmaceth";
		rockchip,grf = <0x17>;
		snps,txpbl = <0x04>;
		status = "okay";
		assigned-clocks = <0x08 0xa6>;
		assigned-clock-parents = <0x18>;
		clock_in_out = "input";
		phy-supply = <0x19>;
		phy-mode = "rgmii";
		pinctrl-names = "default";
		pinctrl-0 = <0x1a>;
		snps,reset-gpio = <0x1b 0x0f 0x01>;
		snps,reset-active-low;
		snps,reset-delays-us = <0x00 0x2710 0xc350>;
		tx_delay = <0x28>;
		rx_delay = <0x11>;
	};

	mmc@fe310000 {
		compatible = "rockchip,rk3399-dw-mshc\0rockchip,rk3288-dw-mshc";
		reg = <0x00 0xfe310000 0x00 0x4000>;
		interrupts = <0x00 0x40 0x04 0x00>;
		max-frequency = <0x8f0d180>;
		clocks = <0x08 0x1ee 0x08 0x4d 0x08 0x9c 0x08 0x9d>;
		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
		fifo-depth = <0x100>;
		power-domains = <0x16 0x1c>;
		resets = <0x08 0x79>;
		reset-names = "reset";
		status = "disabled";
	};

	mmc@fe320000 {
		compatible = "rockchip,rk3399-dw-mshc\0rockchip,rk3288-dw-mshc";
		reg = <0x00 0xfe320000 0x00 0x4000>;
		interrupts = <0x00 0x41 0x04 0x00>;
		max-frequency = <0x8f0d180>;
		assigned-clocks = <0x08 0x1cd>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x08 0x1ce 0x08 0x4c 0x08 0x9a 0x08 0x9b>;
		clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
		fifo-depth = <0x100>;
		power-domains = <0x16 0x1b>;
		resets = <0x08 0x7a>;
		reset-names = "reset";
		status = "okay";
		bus-width = <0x04>;
		cap-sd-highspeed;
		cd-gpios = <0x1c 0x07 0x01>;
		disable-wp;
		pinctrl-names = "default";
		pinctrl-0 = <0x1d 0x1e 0x1f>;
		sd-uhs-sdr104;
		vmmc-supply = <0x20>;
		vqmmc-supply = <0x21>;
		u-boot,dm-pre-reloc;
		u-boot,spl-fifo-mode;
	};

	mmc@fe330000 {
		compatible = "rockchip,rk3399-sdhci-5.1\0arasan,sdhci-5.1";
		reg = <0x00 0xfe330000 0x00 0x10000>;
		interrupts = <0x00 0x0b 0x04 0x00>;
		arasan,soc-ctl-syscon = <0x17>;
		assigned-clocks = <0x08 0x4e>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x08 0x4e 0x08 0xf0>;
		clock-names = "clk_xin\0clk_ahb";
		clock-output-names = "emmc_cardclock";
		#clock-cells = <0x00>;
		phys = <0x22>;
		phy-names = "phy_arasan";
		power-domains = <0x16 0x17>;
		disable-cqe-dcmd;
		status = "okay";
		bus-width = <0x08>;
		non-removable;
		max-frequency = <0xbebc200>;
		u-boot,dm-pre-reloc;
		phandle = <0x89>;
	};

	usb@fe380000 {
		compatible = "generic-ehci";
		reg = <0x00 0xfe380000 0x00 0x20000>;
		interrupts = <0x00 0x1a 0x04 0x00>;
		clocks = <0x08 0x1c8 0x08 0x1c9 0x23>;
		phys = <0x24>;
		phy-names = "usb";
		status = "okay";
	};

	usb@fe3a0000 {
		compatible = "generic-ohci";
		reg = <0x00 0xfe3a0000 0x00 0x20000>;
		interrupts = <0x00 0x1c 0x04 0x00>;
		clocks = <0x08 0x1c8 0x08 0x1c9 0x23>;
		phys = <0x24>;
		phy-names = "usb";
		status = "okay";
	};

	usb@fe3c0000 {
		compatible = "generic-ehci";
		reg = <0x00 0xfe3c0000 0x00 0x20000>;
		interrupts = <0x00 0x1e 0x04 0x00>;
		clocks = <0x08 0x1ca 0x08 0x1cb 0x25>;
		phys = <0x26>;
		phy-names = "usb";
		status = "okay";
	};

	usb@fe3e0000 {
		compatible = "generic-ohci";
		reg = <0x00 0xfe3e0000 0x00 0x20000>;
		interrupts = <0x00 0x20 0x04 0x00>;
		clocks = <0x08 0x1ca 0x08 0x1cb 0x25>;
		phys = <0x26>;
		phy-names = "usb";
		status = "okay";
	};

	usb@fe800000 {
		compatible = "rockchip,rk3399-dwc3";
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		clocks = <0x08 0x81 0x08 0x83 0x08 0xf6 0x08 0xf8 0x08 0xf4 0x08 0xf9>;
		clock-names = "ref_clk\0suspend_clk\0bus_clk\0aclk_usb3_rksoc_axi_perf\0aclk_usb3\0grf_clk";
		resets = <0x08 0x125>;
		reset-names = "usb3-otg";
		status = "okay";

		usb@fe800000 {
			compatible = "snps,dwc3";
			reg = <0x00 0xfe800000 0x00 0x100000>;
			interrupts = <0x00 0x69 0x04 0x00>;
			clocks = <0x08 0x81 0x08 0xf6 0x08 0x83>;
			clock-names = "ref\0bus_early\0suspend";
			dr_mode = "otg";
			phys = <0x27 0x28>;
			phy-names = "usb2-phy\0usb3-phy";
			phy_type = "utmi_wide";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			power-domains = <0x16 0x18>;
			status = "okay";
		};
	};

	usb@fe900000 {
		compatible = "rockchip,rk3399-dwc3";
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		clocks = <0x08 0x82 0x08 0x84 0x08 0xf7 0x08 0xf8 0x08 0xf4 0x08 0xf9>;
		clock-names = "ref_clk\0suspend_clk\0bus_clk\0aclk_usb3_rksoc_axi_perf\0aclk_usb3\0grf_clk";
		resets = <0x08 0x126>;
		reset-names = "usb3-otg";
		status = "okay";

		usb@fe900000 {
			compatible = "snps,dwc3";
			reg = <0x00 0xfe900000 0x00 0x100000>;
			interrupts = <0x00 0x6e 0x04 0x00>;
			clocks = <0x08 0x82 0x08 0xf7 0x08 0x84>;
			clock-names = "ref\0bus_early\0suspend";
			dr_mode = "host";
			phys = <0x29 0x2a>;
			phy-names = "usb2-phy\0usb3-phy";
			phy_type = "utmi_wide";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,dis-tx-ipgap-linecheck-quirk;
			power-domains = <0x16 0x18>;
			status = "okay";
		};
	};

	dp@fec00000 {
		compatible = "rockchip,rk3399-cdn-dp";
		reg = <0x00 0xfec00000 0x00 0x100000>;
		interrupts = <0x00 0x09 0x04 0x00>;
		assigned-clocks = <0x08 0x72 0x08 0xa1>;
		assigned-clock-rates = <0x5f5e100 0xbebc200>;
		clocks = <0x08 0x72 0x08 0x175 0x08 0xa1 0x08 0x16f>;
		clock-names = "core-clk\0pclk\0spdif\0grf";
		phys = <0x2b 0x2c>;
		power-domains = <0x16 0x15>;
		resets = <0x08 0x103 0x08 0x148 0x08 0x14a 0x08 0xfd>;
		reset-names = "spdif\0dptx\0apb\0core";
		rockchip,grf = <0x17>;
		#sound-dai-cells = <0x01>;
		status = "disabled";

		ports {

			port {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x2d>;
					phandle = <0x98>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0x2e>;
					phandle = <0x92>;
				};
			};
		};
	};

	interrupt-controller@fee00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <0x04>;
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		interrupt-controller;
		reg = <0x00 0xfee00000 0x00 0x10000 0x00 0xfef00000 0x00 0xc0000 0x00 0xfff00000 0x00 0x10000 0x00 0xfff10000 0x00 0x10000 0x00 0xfff20000 0x00 0x10000>;
		interrupts = <0x01 0x09 0x04 0x00>;
		phandle = <0x01>;

		interrupt-controller@fee20000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <0x01>;
			reg = <0x00 0xfee20000 0x00 0x20000>;
			phandle = <0x14>;
		};

		ppi-partitions {

			interrupt-partition-0 {
				affinity = <0x02 0x03 0x04 0x05>;
				phandle = <0x11>;
			};

			interrupt-partition-1 {
				affinity = <0x06 0x07>;
				phandle = <0x12>;
			};
		};
	};

	saradc@ff100000 {
		compatible = "rockchip,rk3399-saradc";
		reg = <0x00 0xff100000 0x00 0x100>;
		interrupts = <0x00 0x3e 0x04 0x00>;
		#io-channel-cells = <0x01>;
		clocks = <0x08 0x50 0x08 0x165>;
		clock-names = "saradc\0apb_pclk";
		resets = <0x08 0xd4>;
		reset-names = "saradc-apb";
		status = "okay";
		vref-supply = <0x2f>;
		phandle = <0xb1>;
	};

	i2c@ff110000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff110000 0x00 0x1000>;
		assigned-clocks = <0x08 0x41>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x08 0x41 0x08 0x155>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x3b 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x30>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		i2c-scl-rising-time-ns = <0x12c>;
		i2c-scl-falling-time-ns = <0x0f>;
	};

	i2c@ff120000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff120000 0x00 0x1000>;
		assigned-clocks = <0x08 0x42>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x08 0x42 0x08 0x156>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x23 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x31>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	i2c@ff130000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff130000 0x00 0x1000>;
		assigned-clocks = <0x08 0x43>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x08 0x43 0x08 0x157>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x22 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x32>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		i2c-scl-rising-time-ns = <0x1c2>;
		i2c-scl-falling-time-ns = <0x0f>;
		phandle = <0x9d>;
	};

	i2c@ff140000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff140000 0x00 0x1000>;
		assigned-clocks = <0x08 0x44>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x08 0x44 0x08 0x158>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x26 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x33>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	i2c@ff150000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff150000 0x00 0x1000>;
		assigned-clocks = <0x08 0x45>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x08 0x45 0x08 0x159>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x25 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x34>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	i2c@ff160000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff160000 0x00 0x1000>;
		assigned-clocks = <0x08 0x46>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x08 0x46 0x08 0x15a>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x24 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x35>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		i2c-scl-rising-time-ns = <0x258>;
		i2c-scl-falling-time-ns = <0x14>;

		usb-typec@22 {
			compatible = "fcs,fusb302";
			reg = <0x22>;
			interrupt-parent = <0x36>;
			interrupts = <0x02 0x08>;
			pinctrl-names = "default";
			pinctrl-0 = <0x37>;
			vbus-supply = <0x38>;
			status = "okay";
		};

		regulator@66 {
			compatible = "mps,mp8859";
			reg = <0x66>;

			mp8859_dcdc {
				regulator-name = "dc_12v";
				regulator-min-microvolt = <0xb71b00>;
				regulator-max-microvolt = <0xb71b00>;
				regulator-always-on;
				regulator-boot-on;
				vin-supply = <0x38>;
				compatible = "regulator-fixed";
				phandle = <0xba>;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <0xb71b00>;
				};
			};
		};
	};

	serial@ff180000 {
		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
		reg = <0x00 0xff180000 0x00 0x100>;
		clocks = <0x08 0x51 0x08 0x160>;
		clock-names = "baudclk\0apb_pclk";
		interrupts = <0x00 0x63 0x04 0x00>;
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x39 0x3a>;
		status = "okay";
		u-boot,dm-pre-reloc;
	};

	serial@ff190000 {
		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
		reg = <0x00 0xff190000 0x00 0x100>;
		clocks = <0x08 0x52 0x08 0x161>;
		clock-names = "baudclk\0apb_pclk";
		interrupts = <0x00 0x62 0x04 0x00>;
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x3b>;
		status = "disabled";
	};

	serial@ff1a0000 {
		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
		reg = <0x00 0xff1a0000 0x00 0x100>;
		clocks = <0x08 0x53 0x08 0x162>;
		clock-names = "baudclk\0apb_pclk";
		interrupts = <0x00 0x64 0x04 0x00>;
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x3c>;
		status = "okay";
		u-boot,dm-pre-reloc;
	};

	serial@ff1b0000 {
		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
		reg = <0x00 0xff1b0000 0x00 0x100>;
		clocks = <0x08 0x54 0x08 0x163>;
		clock-names = "baudclk\0apb_pclk";
		interrupts = <0x00 0x65 0x04 0x00>;
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x3d>;
		status = "disabled";
	};

	spi@ff1c0000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff1c0000 0x00 0x1000>;
		clocks = <0x08 0x47 0x08 0x15b>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x44 0x04 0x00>;
		dmas = <0x3e 0x0a 0x3e 0x0b>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x3f 0x40 0x41 0x42>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	spi@ff1d0000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff1d0000 0x00 0x1000>;
		clocks = <0x08 0x48 0x08 0x15c>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x35 0x04 0x00>;
		dmas = <0x3e 0x0c 0x3e 0x0d>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x43 0x44 0x45 0x46>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		u-boot,dm-pre-reloc;

		flash@0 {
			compatible = "jedec,spi-nor";
			reg = <0x00>;
			spi-max-frequency = <0x989680>;
			u-boot,dm-pre-reloc;
		};
	};

	spi@ff1e0000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff1e0000 0x00 0x1000>;
		clocks = <0x08 0x49 0x08 0x15d>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x34 0x04 0x00>;
		dmas = <0x3e 0x0e 0x3e 0x0f>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x47 0x48 0x49 0x4a>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	spi@ff1f0000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff1f0000 0x00 0x1000>;
		clocks = <0x08 0x4a 0x08 0x15e>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x43 0x04 0x00>;
		dmas = <0x3e 0x12 0x3e 0x13>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x4b 0x4c 0x4d 0x4e>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	spi@ff200000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff200000 0x00 0x1000>;
		clocks = <0x08 0x4b 0x08 0x15f>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x84 0x04 0x00>;
		dmas = <0x4f 0x08 0x4f 0x09>;
		dma-names = "tx\0rx";
		pinctrl-names = "default";
		pinctrl-0 = <0x50 0x51 0x52 0x53>;
		power-domains = <0x16 0x1c>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	thermal-zones {

		cpu-thermal {
			polling-delay-passive = <0x64>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x54 0x00>;

			trips {

				cpu_alert0 {
					temperature = <0x11170>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x55>;
				};

				cpu_alert1 {
					temperature = <0x124f8>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x56>;
				};

				cpu_crit {
					temperature = <0x17318>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};

			cooling-maps {

				map0 {
					trip = <0x55>;
					cooling-device = <0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff>;
				};

				map1 {
					trip = <0x56>;
					cooling-device = <0x02 0xffffffff 0xffffffff 0x03 0xffffffff 0xffffffff 0x04 0xffffffff 0xffffffff 0x05 0xffffffff 0xffffffff 0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff>;
				};
			};
		};

		gpu-thermal {
			polling-delay-passive = <0x64>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x54 0x01>;

			trips {

				gpu_alert0 {
					temperature = <0x124f8>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x57>;
				};

				gpu_crit {
					temperature = <0x17318>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};

			cooling-maps {

				map0 {
					trip = <0x57>;
					cooling-device = <0x58 0xffffffff 0xffffffff>;
				};
			};
		};
	};

	tsadc@ff260000 {
		compatible = "rockchip,rk3399-tsadc";
		reg = <0x00 0xff260000 0x00 0x100>;
		interrupts = <0x00 0x61 0x04 0x00>;
		assigned-clocks = <0x08 0x4f>;
		assigned-clock-rates = <0xb71b0>;
		clocks = <0x08 0x4f 0x08 0x164>;
		clock-names = "tsadc\0apb_pclk";
		resets = <0x08 0xe8>;
		reset-names = "tsadc-apb";
		rockchip,grf = <0x17>;
		rockchip,hw-tshut-temp = <0x17318>;
		pinctrl-names = "init\0default\0sleep";
		pinctrl-0 = <0x59>;
		pinctrl-1 = <0x5a>;
		pinctrl-2 = <0x59>;
		#thermal-sensor-cells = <0x01>;
		status = "okay";
		rockchip,hw-tshut-mode = <0x01>;
		rockchip,hw-tshut-polarity = <0x01>;
		phandle = <0x54>;
	};

	qos@ffa58000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa58000 0x00 0x20>;
		phandle = <0x62>;
	};

	qos@ffa5c000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa5c000 0x00 0x20>;
		phandle = <0x63>;
	};

	qos@ffa60080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa60080 0x00 0x20>;
	};

	qos@ffa60100 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa60100 0x00 0x20>;
	};

	qos@ffa60180 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa60180 0x00 0x20>;
	};

	qos@ffa70000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa70000 0x00 0x20>;
		phandle = <0x66>;
	};

	qos@ffa70080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa70080 0x00 0x20>;
		phandle = <0x67>;
	};

	qos@ffa74000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa74000 0x00 0x20>;
		phandle = <0x64>;
	};

	qos@ffa76000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa76000 0x00 0x20>;
		phandle = <0x65>;
	};

	qos@ffa90000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa90000 0x00 0x20>;
		phandle = <0x68>;
	};

	qos@ffa98000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffa98000 0x00 0x20>;
		phandle = <0x5b>;
	};

	qos@ffaa0000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffaa0000 0x00 0x20>;
		phandle = <0x69>;
	};

	qos@ffaa0080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffaa0080 0x00 0x20>;
		phandle = <0x6a>;
	};

	qos@ffaa8000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffaa8000 0x00 0x20>;
		phandle = <0x6b>;
	};

	qos@ffaa8080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffaa8080 0x00 0x20>;
		phandle = <0x6c>;
	};

	qos@ffab0000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffab0000 0x00 0x20>;
		phandle = <0x5c>;
	};

	qos@ffab0080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffab0080 0x00 0x20>;
		phandle = <0x5d>;
	};

	qos@ffab8000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffab8000 0x00 0x20>;
		phandle = <0x5e>;
	};

	qos@ffac0000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffac0000 0x00 0x20>;
		phandle = <0x5f>;
	};

	qos@ffac0080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffac0080 0x00 0x20>;
		phandle = <0x60>;
	};

	qos@ffac8000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffac8000 0x00 0x20>;
		phandle = <0x6d>;
	};

	qos@ffac8080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffac8080 0x00 0x20>;
		phandle = <0x6e>;
	};

	qos@ffad0000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffad0000 0x00 0x20>;
		phandle = <0x6f>;
	};

	qos@ffad8080 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffad8080 0x00 0x20>;
	};

	qos@ffae0000 {
		compatible = "rockchip,rk3399-qos\0syscon";
		reg = <0x00 0xffae0000 0x00 0x20>;
		phandle = <0x61>;
	};

	power-management@ff310000 {
		compatible = "rockchip,rk3399-pmu\0syscon\0simple-mfd";
		reg = <0x00 0xff310000 0x00 0x1000>;
		u-boot,dm-pre-reloc;

		power-controller {
			compatible = "rockchip,rk3399-power-controller";
			#power-domain-cells = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x16>;

			power-domain@34 {
				reg = <0x22>;
				clocks = <0x08 0xe1 0x08 0x1dd>;
				pm_qos = <0x5b>;
				#power-domain-cells = <0x00>;
			};

			power-domain@33 {
				reg = <0x21>;
				clocks = <0x08 0xdc 0x08 0x1e5>;
				pm_qos = <0x5c 0x5d>;
				#power-domain-cells = <0x00>;
			};

			power-domain@31 {
				reg = <0x1f>;
				clocks = <0x08 0xeb 0x08 0x1ea>;
				pm_qos = <0x5e>;
				#power-domain-cells = <0x00>;
			};

			power-domain@32 {
				reg = <0x20>;
				clocks = <0x08 0xed 0x08 0x1ec>;
				pm_qos = <0x5f 0x60>;
				#power-domain-cells = <0x00>;
			};

			power-domain@35 {
				reg = <0x23>;
				clocks = <0x08 0xd0>;
				pm_qos = <0x61>;
				#power-domain-cells = <0x00>;
			};

			power-domain@25 {
				reg = <0x19>;
				clocks = <0x08 0x16c>;
				#power-domain-cells = <0x00>;
			};

			power-domain@23 {
				reg = <0x17>;
				clocks = <0x08 0xf0>;
				pm_qos = <0x62>;
				#power-domain-cells = <0x00>;
			};

			power-domain@22 {
				reg = <0x16>;
				clocks = <0x08 0xd5 0x08 0x166>;
				pm_qos = <0x63>;
				#power-domain-cells = <0x00>;
			};

			power-domain@27 {
				reg = <0x1b>;
				clocks = <0x08 0x1ce 0x08 0x4c>;
				pm_qos = <0x64>;
				#power-domain-cells = <0x00>;
			};

			power-domain@28 {
				reg = <0x1c>;
				clocks = <0x08 0x1ee>;
				pm_qos = <0x65>;
				#power-domain-cells = <0x00>;
			};

			power-domain@8 {
				reg = <0x08>;
				clocks = <0x08 0x7e 0x08 0x7d>;
				#power-domain-cells = <0x00>;
			};

			power-domain@9 {
				reg = <0x09>;
				clocks = <0x08 0x80 0x08 0x7f>;
				#power-domain-cells = <0x00>;
			};

			power-domain@24 {
				reg = <0x18>;
				clocks = <0x08 0xf4>;
				pm_qos = <0x66 0x67>;
				#power-domain-cells = <0x00>;
			};

			power-domain@15 {
				reg = <0x0f>;
				#power-domain-cells = <0x01>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				power-domain@21 {
					reg = <0x15>;
					clocks = <0x08 0xde 0x08 0x1e7 0x08 0x172>;
					pm_qos = <0x68>;
					#power-domain-cells = <0x00>;
				};

				power-domain@19 {
					reg = <0x13>;
					clocks = <0x08 0xe5 0x08 0x1df>;
					pm_qos = <0x69 0x6a>;
					#power-domain-cells = <0x00>;
				};

				power-domain@20 {
					reg = <0x14>;
					clocks = <0x08 0xe6 0x08 0x1e0>;
					pm_qos = <0x6b 0x6c>;
					#power-domain-cells = <0x00>;
				};

				power-domain@16 {
					reg = <0x10>;
					#power-domain-cells = <0x01>;
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					power-domain@17 {
						reg = <0x11>;
						clocks = <0x08 0xd9 0x08 0x1d9>;
						pm_qos = <0x6d 0x6e>;
						#power-domain-cells = <0x00>;
					};

					power-domain@18 {
						reg = <0x12>;
						clocks = <0x08 0xdb 0x08 0x1db>;
						pm_qos = <0x6f>;
						#power-domain-cells = <0x00>;
					};
				};
			};
		};
	};

	syscon@ff320000 {
		compatible = "rockchip,rk3399-pmugrf\0syscon\0simple-mfd";
		reg = <0x00 0xff320000 0x00 0x1000>;
		u-boot,dm-pre-reloc;
		phandle = <0x86>;

		io-domains {
			compatible = "rockchip,rk3399-pmu-io-voltage-domain";
			status = "okay";
			pmu1830-supply = <0x70>;
		};
	};

	spi@ff350000 {
		compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi";
		reg = <0x00 0xff350000 0x00 0x1000>;
		clocks = <0x71 0x03 0x71 0x1f>;
		clock-names = "spiclk\0apb_pclk";
		interrupts = <0x00 0x3c 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x72 0x73 0x74 0x75>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	serial@ff370000 {
		compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart";
		reg = <0x00 0xff370000 0x00 0x100>;
		clocks = <0x71 0x06 0x71 0x22>;
		clock-names = "baudclk\0apb_pclk";
		interrupts = <0x00 0x66 0x04 0x00>;
		reg-shift = <0x02>;
		reg-io-width = <0x04>;
		pinctrl-names = "default";
		pinctrl-0 = <0x76>;
		status = "disabled";
	};

	i2c@ff3c0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff3c0000 0x00 0x1000>;
		assigned-clocks = <0x71 0x09>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x71 0x09 0x71 0x1b>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x39 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x77>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		clock-frequency = <0x61a80>;
		i2c-scl-rising-time-ns = <0xa8>;
		i2c-scl-falling-time-ns = <0x04>;

		pmic@1b {
			compatible = "rockchip,rk808";
			reg = <0x1b>;
			interrupt-parent = <0x36>;
			interrupts = <0x15 0x08>;
			#clock-cells = <0x01>;
			clock-output-names = "xin32k\0rk808-clkout2";
			pinctrl-names = "default";
			pinctrl-0 = <0x78>;
			rockchip,system-power-controller;
			wakeup-source;
			vcc1-supply = <0x79>;
			vcc2-supply = <0x79>;
			vcc3-supply = <0x79>;
			vcc4-supply = <0x79>;
			vcc6-supply = <0x79>;
			vcc7-supply = <0x79>;
			vcc8-supply = <0x79>;
			vcc9-supply = <0x79>;
			vcc10-supply = <0x79>;
			vcc11-supply = <0x79>;
			vcc12-supply = <0x79>;
			vcc13-supply = <0x79>;
			vcc14-supply = <0x79>;
			vddio-supply = <0x70>;
			phandle = <0xb8>;

			regulators {

				DCDC_REG1 {
					regulator-name = "vdd_center";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xb71b0>;
					regulator-max-microvolt = <0x149970>;
					regulator-ramp-delay = <0x1771>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				DCDC_REG2 {
					regulator-name = "vdd_cpu_l";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xb71b0>;
					regulator-max-microvolt = <0x149970>;
					regulator-ramp-delay = <0x1771>;
					phandle = <0x0c>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				DCDC_REG3 {
					regulator-name = "vcc_ddr";
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-on-in-suspend;
					};
				};

				DCDC_REG4 {
					regulator-name = "vcc_1v8";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					phandle = <0xbb>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x1b7740>;
					};
				};

				LDO_REG1 {
					regulator-name = "vcca1v8_codec";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					phandle = <0x87>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG2 {
					regulator-name = "vcc1v8_hdmi";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG3 {
					regulator-name = "vcc1v8_pmu";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x1b7740>;
					};
				};

				LDO_REG4 {
					regulator-name = "vcc_sdio";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x2dc6c0>;
					phandle = <0x21>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x2dc6c0>;
					};
				};

				LDO_REG5 {
					regulator-name = "vcca3v0_codec";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x2dc6c0>;
					regulator-max-microvolt = <0x2dc6c0>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG6 {
					regulator-name = "vcc_1v5";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x16e360>;
					regulator-max-microvolt = <0x16e360>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x16e360>;
					};
				};

				LDO_REG7 {
					regulator-name = "vcca0v9_hdmi";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xdbba0>;
					regulator-max-microvolt = <0xdbba0>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				LDO_REG8 {
					regulator-name = "vcc_3v0";
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x2dc6c0>;
					regulator-max-microvolt = <0x2dc6c0>;
					phandle = <0x70>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x2dc6c0>;
					};
				};

				SWITCH_REG1 {
					regulator-name = "vcc3v3_s3";
					regulator-always-on;
					regulator-boot-on;
					phandle = <0x19>;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};

				SWITCH_REG2 {
					regulator-name = "vcc3v3_s0";
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-off-in-suspend;
					};
				};
			};
		};

		regulator@40 {
			compatible = "silergy,syr827";
			reg = <0x40>;
			fcs,suspend-voltage-selector = <0x01>;
			pinctrl-names = "default";
			pinctrl-0 = <0x7a>;
			regulator-name = "vdd_cpu_b";
			regulator-min-microvolt = <0xadf34>;
			regulator-max-microvolt = <0x16e360>;
			regulator-ramp-delay = <0x3e8>;
			regulator-always-on;
			regulator-boot-on;
			vin-supply = <0x79>;
			phandle = <0x0e>;

			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};

		regulator@41 {
			compatible = "silergy,syr828";
			reg = <0x41>;
			fcs,suspend-voltage-selector = <0x01>;
			pinctrl-names = "default";
			pinctrl-0 = <0x7b>;
			regulator-name = "vdd_gpu";
			regulator-min-microvolt = <0xadf34>;
			regulator-max-microvolt = <0x16e360>;
			regulator-ramp-delay = <0x3e8>;
			regulator-always-on;
			regulator-boot-on;
			vin-supply = <0x79>;
			phandle = <0xa9>;

			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};
	};

	i2c@ff3d0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff3d0000 0x00 0x1000>;
		assigned-clocks = <0x71 0x0a>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x71 0x0a 0x71 0x1c>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x38 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x7c>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "okay";
		i2c-scl-rising-time-ns = <0x258>;
		i2c-scl-falling-time-ns = <0x14>;

		usb-typec@22 {
			compatible = "fcs,fusb302";
			reg = <0x22>;
			interrupt-parent = <0x36>;
			interrupts = <0x01 0x08>;
			pinctrl-names = "default";
			pinctrl-0 = <0x7d>;
			vbus-supply = <0x7e>;
			status = "okay";
		};
	};

	i2c@ff3e0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x00 0xff3e0000 0x00 0x1000>;
		assigned-clocks = <0x71 0x0b>;
		assigned-clock-rates = <0xbebc200>;
		clocks = <0x71 0x0b 0x71 0x1d>;
		clock-names = "i2c\0pclk";
		interrupts = <0x00 0x3a 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0x7f>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";
	};

	pwm@ff420000 {
		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
		reg = <0x00 0xff420000 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "default";
		pinctrl-0 = <0x80>;
		clocks = <0x71 0x1e>;
		status = "okay";
		phandle = <0xb0>;
	};

	pwm@ff420010 {
		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
		reg = <0x00 0xff420010 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "default";
		pinctrl-0 = <0x81>;
		clocks = <0x71 0x1e>;
		status = "disabled";
	};

	pwm@ff420020 {
		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
		reg = <0x00 0xff420020 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "default";
		pinctrl-0 = <0x82>;
		clocks = <0x71 0x1e>;
		status = "okay";
		phandle = <0xc4>;
	};

	pwm@ff420030 {
		compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm";
		reg = <0x00 0xff420030 0x00 0x10>;
		#pwm-cells = <0x03>;
		pinctrl-names = "default";
		pinctrl-0 = <0x83>;
		clocks = <0x71 0x1e>;
		status = "disabled";
	};

	video-codec@ff650000 {
		compatible = "rockchip,rk3399-vpu";
		reg = <0x00 0xff650000 0x00 0x800>;
		interrupts = <0x00 0x72 0x04 0x00 0x00 0x71 0x04 0x00>;
		interrupt-names = "vepu\0vdpu";
		clocks = <0x08 0xeb 0x08 0x1ea>;
		clock-names = "aclk\0hclk";
		iommus = <0x84>;
		power-domains = <0x16 0x1f>;
	};

	iommu@ff650800 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff650800 0x00 0x40>;
		interrupts = <0x00 0x73 0x04 0x00>;
		interrupt-names = "vpu_mmu";
		clocks = <0x08 0xeb 0x08 0x1ea>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		power-domains = <0x16 0x1f>;
		phandle = <0x84>;
	};

	video-codec@ff660000 {
		compatible = "rockchip,rk3399-vdec";
		reg = <0x00 0xff660000 0x00 0x400>;
		interrupts = <0x00 0x74 0x04 0x00>;
		clocks = <0x08 0xed 0x08 0x1ec 0x08 0x9f 0x08 0x9e>;
		clock-names = "axi\0ahb\0cabac\0core";
		iommus = <0x85>;
		power-domains = <0x16 0x20>;
	};

	iommu@ff660480 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff660480 0x00 0x40 0x00 0xff6604c0 0x00 0x40>;
		interrupts = <0x00 0x75 0x04 0x00>;
		interrupt-names = "vdec_mmu";
		clocks = <0x08 0xed 0x08 0x1ec>;
		clock-names = "aclk\0iface";
		power-domains = <0x16 0x20>;
		#iommu-cells = <0x00>;
		phandle = <0x85>;
	};

	iommu@ff670800 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff670800 0x00 0x40>;
		interrupts = <0x00 0x2a 0x04 0x00>;
		interrupt-names = "iep_mmu";
		clocks = <0x08 0xe1 0x08 0x1dd>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		status = "disabled";
	};

	rga@ff680000 {
		compatible = "rockchip,rk3399-rga";
		reg = <0x00 0xff680000 0x00 0x10000>;
		interrupts = <0x00 0x37 0x04 0x00>;
		clocks = <0x08 0xdc 0x08 0x1e5 0x08 0x6d>;
		clock-names = "aclk\0hclk\0sclk";
		resets = <0x08 0x6a 0x08 0x67 0x08 0x69>;
		reset-names = "core\0axi\0ahb";
		power-domains = <0x16 0x21>;
	};

	efuse@ff690000 {
		compatible = "rockchip,rk3399-efuse";
		reg = <0x00 0xff690000 0x00 0x80>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		clocks = <0x08 0x17d>;
		clock-names = "pclk_efuse";

		cpu-id@7 {
			reg = <0x07 0x10>;
		};

		cpu-leakage@17 {
			reg = <0x17 0x01>;
		};

		gpu-leakage@18 {
			reg = <0x18 0x01>;
		};

		center-leakage@19 {
			reg = <0x19 0x01>;
		};

		cpu-leakage@1a {
			reg = <0x1a 0x01>;
		};

		logic-leakage@1b {
			reg = <0x1b 0x01>;
		};

		wafer-info@1c {
			reg = <0x1c 0x01>;
		};
	};

	dma-controller@ff6d0000 {
		compatible = "arm,pl330\0arm,primecell";
		reg = <0x00 0xff6d0000 0x00 0x4000>;
		interrupts = <0x00 0x05 0x04 0x00 0x00 0x06 0x04 0x00>;
		#dma-cells = <0x01>;
		arm,pl330-periph-burst;
		clocks = <0x08 0xd3>;
		clock-names = "apb_pclk";
		phandle = <0x4f>;
	};

	dma-controller@ff6e0000 {
		compatible = "arm,pl330\0arm,primecell";
		reg = <0x00 0xff6e0000 0x00 0x4000>;
		interrupts = <0x00 0x07 0x04 0x00 0x00 0x08 0x04 0x00>;
		#dma-cells = <0x01>;
		arm,pl330-periph-burst;
		clocks = <0x08 0xd4>;
		clock-names = "apb_pclk";
		phandle = <0x3e>;
	};

	pmu-clock-controller@ff750000 {
		compatible = "rockchip,rk3399-pmucru";
		reg = <0x00 0xff750000 0x00 0x1000>;
		rockchip,grf = <0x86>;
		#clock-cells = <0x01>;
		#reset-cells = <0x01>;
		assigned-clocks = <0x71 0x01>;
		assigned-clock-rates = <0x284af100>;
		u-boot,dm-pre-reloc;
		phandle = <0x71>;
	};

	clock-controller@ff760000 {
		compatible = "rockchip,rk3399-cru";
		reg = <0x00 0xff760000 0x00 0x1000>;
		rockchip,grf = <0x17>;
		#clock-cells = <0x01>;
		#reset-cells = <0x01>;
		assigned-clocks = <0x08 0x05 0x08 0x04 0x08 0x06 0x08 0xc0 0x08 0x1c0 0x08 0x140 0x08 0xc2 0x08 0x1c1 0x08 0x142 0x08 0xc9 0x08 0x1c2 0x08 0x143 0x08 0xe3 0x08 0xde 0x08 0x106 0x08 0x178>;
		assigned-clock-rates = <0x2367b880 0x2faf0800 0x3b9aca00 0x8f0d180 0x47868c0 0x23c3460 0x5f5e100 0x5f5e100 0x2faf080 0x23c34600 0x5f5e100 0x2faf080 0x17d78400 0x17d78400 0xbebc200 0xbebc200>;
		u-boot,dm-pre-reloc;
		phandle = <0x08>;
	};

	syscon@ff770000 {
		compatible = "rockchip,rk3399-grf\0syscon\0simple-mfd";
		reg = <0x00 0xff770000 0x00 0x10000>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		u-boot,dm-pre-reloc;
		phandle = <0x17>;

		io-domains {
			compatible = "rockchip,rk3399-io-voltage-domain";
			status = "okay";
			audio-supply = <0x87>;
			bt656-supply = <0x70>;
			gpio1830-supply = <0x70>;
			sdmmc-supply = <0x21>;
		};

		mipi-dphy-rx0 {
			compatible = "rockchip,rk3399-mipi-dphy-rx0";
			clocks = <0x08 0x77 0x08 0xa5 0x08 0x16f>;
			clock-names = "dphy-ref\0dphy-cfg\0grf";
			power-domains = <0x16 0x0f>;
			#phy-cells = <0x00>;
			status = "disabled";
			phandle = <0x9a>;
		};

		usb2phy@e450 {
			compatible = "rockchip,rk3399-usb2phy";
			reg = <0xe450 0x10>;
			clocks = <0x08 0x7b>;
			clock-names = "phyclk";
			#clock-cells = <0x00>;
			clock-output-names = "clk_usbphy0_480m";
			status = "okay";
			phandle = <0x23>;

			host-port {
				#phy-cells = <0x00>;
				interrupts = <0x00 0x1b 0x04 0x00>;
				interrupt-names = "linestate";
				status = "okay";
				phy-supply = <0x88>;
				phandle = <0x24>;
			};

			otg-port {
				#phy-cells = <0x00>;
				interrupts = <0x00 0x67 0x04 0x00 0x00 0x68 0x04 0x00 0x00 0x6a 0x04 0x00>;
				interrupt-names = "otg-bvalid\0otg-id\0linestate";
				status = "okay";
				phy-supply = <0x38>;
				phandle = <0x27>;
			};
		};

		usb2phy@e460 {
			compatible = "rockchip,rk3399-usb2phy";
			reg = <0xe460 0x10>;
			clocks = <0x08 0x7c>;
			clock-names = "phyclk";
			#clock-cells = <0x00>;
			clock-output-names = "clk_usbphy1_480m";
			status = "okay";
			phandle = <0x25>;

			host-port {
				#phy-cells = <0x00>;
				interrupts = <0x00 0x1f 0x04 0x00>;
				interrupt-names = "linestate";
				status = "okay";
				phy-supply = <0x88>;
				phandle = <0x26>;
			};

			otg-port {
				#phy-cells = <0x00>;
				interrupts = <0x00 0x6c 0x04 0x00 0x00 0x6d 0x04 0x00 0x00 0x6f 0x04 0x00>;
				interrupt-names = "otg-bvalid\0otg-id\0linestate";
				status = "okay";
				phy-supply = <0x7e>;
				phandle = <0x29>;
			};
		};

		phy@f780 {
			compatible = "rockchip,rk3399-emmc-phy";
			reg = <0xf780 0x24>;
			clocks = <0x89>;
			clock-names = "emmcclk";
			#phy-cells = <0x00>;
			status = "okay";
			u-boot,dm-pre-reloc;
			phandle = <0x22>;
		};

		pcie-phy {
			compatible = "rockchip,rk3399-pcie-phy";
			clocks = <0x08 0x8a>;
			clock-names = "refclk";
			#phy-cells = <0x01>;
			resets = <0x08 0x87>;
			drive-impedance-ohm = <0x32>;
			reset-names = "phy";
			status = "disabled";
			phandle = <0x15>;
		};
	};

	phy@ff7c0000 {
		compatible = "rockchip,rk3399-typec-phy";
		reg = <0x00 0xff7c0000 0x00 0x40000>;
		clocks = <0x08 0x7e 0x08 0x7d>;
		clock-names = "tcpdcore\0tcpdphy-ref";
		assigned-clocks = <0x08 0x7e>;
		assigned-clock-rates = <0x2faf080>;
		power-domains = <0x16 0x08>;
		resets = <0x08 0x95 0x08 0x94 0x08 0x14c>;
		reset-names = "uphy\0uphy-pipe\0uphy-tcphy";
		rockchip,grf = <0x17>;
		status = "okay";

		dp-port {
			#phy-cells = <0x00>;
			phandle = <0x2b>;
		};

		usb3-port {
			#phy-cells = <0x00>;
			phandle = <0x28>;
		};
	};

	phy@ff800000 {
		compatible = "rockchip,rk3399-typec-phy";
		reg = <0x00 0xff800000 0x00 0x40000>;
		clocks = <0x08 0x80 0x08 0x7f>;
		clock-names = "tcpdcore\0tcpdphy-ref";
		assigned-clocks = <0x08 0x80>;
		assigned-clock-rates = <0x2faf080>;
		power-domains = <0x16 0x09>;
		resets = <0x08 0x9d 0x08 0x9c 0x08 0x14d>;
		reset-names = "uphy\0uphy-pipe\0uphy-tcphy";
		rockchip,grf = <0x17>;
		status = "okay";

		dp-port {
			#phy-cells = <0x00>;
			phandle = <0x2c>;
		};

		usb3-port {
			#phy-cells = <0x00>;
			phandle = <0x2a>;
		};
	};

	watchdog@ff848000 {
		compatible = "rockchip,rk3399-wdt\0snps,dw-wdt";
		reg = <0x00 0xff848000 0x00 0x100>;
		clocks = <0x08 0x17c>;
		interrupts = <0x00 0x78 0x04 0x00>;
	};

	rktimer@ff850000 {
		compatible = "rockchip,rk3399-timer";
		reg = <0x00 0xff850000 0x00 0x1000>;
		interrupts = <0x00 0x51 0x04 0x00>;
		clocks = <0x08 0x168 0x08 0x5a>;
		clock-names = "pclk\0timer";
	};

	spdif@ff870000 {
		compatible = "rockchip,rk3399-spdif";
		reg = <0x00 0xff870000 0x00 0x1000>;
		interrupts = <0x00 0x42 0x04 0x00>;
		dmas = <0x4f 0x07>;
		dma-names = "tx";
		clock-names = "mclk\0hclk";
		clocks = <0x08 0x55 0x08 0x1d7>;
		pinctrl-names = "default";
		pinctrl-0 = <0x8a>;
		power-domains = <0x16 0x1c>;
		#sound-dai-cells = <0x00>;
		status = "disabled";
	};

	i2s@ff880000 {
		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
		reg = <0x00 0xff880000 0x00 0x1000>;
		rockchip,grf = <0x17>;
		interrupts = <0x00 0x27 0x04 0x00>;
		dmas = <0x4f 0x00 0x4f 0x01>;
		dma-names = "tx\0rx";
		clock-names = "i2s_clk\0i2s_hclk";
		clocks = <0x08 0x56 0x08 0x1d4>;
		pinctrl-names = "default";
		pinctrl-0 = <0x8b>;
		power-domains = <0x16 0x1c>;
		#sound-dai-cells = <0x00>;
		status = "okay";
		rockchip,playback-channels = <0x08>;
		rockchip,capture-channels = <0x08>;
	};

	i2s@ff890000 {
		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
		reg = <0x00 0xff890000 0x00 0x1000>;
		interrupts = <0x00 0x28 0x04 0x00>;
		dmas = <0x4f 0x02 0x4f 0x03>;
		dma-names = "tx\0rx";
		clock-names = "i2s_clk\0i2s_hclk";
		clocks = <0x08 0x57 0x08 0x1d5>;
		pinctrl-names = "default";
		pinctrl-0 = <0x8c>;
		power-domains = <0x16 0x1c>;
		#sound-dai-cells = <0x00>;
		status = "okay";
		rockchip,playback-channels = <0x02>;
		rockchip,capture-channels = <0x02>;
	};

	i2s@ff8a0000 {
		compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s";
		reg = <0x00 0xff8a0000 0x00 0x1000>;
		interrupts = <0x00 0x29 0x04 0x00>;
		dmas = <0x4f 0x04 0x4f 0x05>;
		dma-names = "tx\0rx";
		clock-names = "i2s_clk\0i2s_hclk";
		clocks = <0x08 0x58 0x08 0x1d6>;
		power-domains = <0x16 0x1c>;
		#sound-dai-cells = <0x00>;
		status = "okay";
		phandle = <0x9b>;
	};

	vop@ff8f0000 {
		compatible = "rockchip,rk3399-vop-lit";
		reg = <0x00 0xff8f0000 0x00 0x3efc>;
		interrupts = <0x00 0x77 0x04 0x00>;
		assigned-clocks = <0x08 0xdb 0x08 0x1db>;
		assigned-clock-rates = <0x17d78400 0x5f5e100>;
		clocks = <0x08 0xdb 0x08 0xb5 0x08 0x1db>;
		clock-names = "aclk_vop\0dclk_vop\0hclk_vop";
		iommus = <0x8d>;
		power-domains = <0x16 0x12>;
		resets = <0x08 0x113 0x08 0x117 0x08 0x119>;
		reset-names = "axi\0ahb\0dclk";
		status = "okay";
		u-boot,dm-pre-reloc;

		port {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x0f>;

			endpoint@0 {
				reg = <0x00>;
				remote-endpoint = <0x8e>;
				phandle = <0xa2>;
			};

			endpoint@1 {
				reg = <0x01>;
				remote-endpoint = <0x8f>;
				phandle = <0xa7>;
			};

			endpoint@2 {
				reg = <0x02>;
				remote-endpoint = <0x90>;
				phandle = <0xa0>;
			};

			endpoint@3 {
				reg = <0x03>;
				remote-endpoint = <0x91>;
				phandle = <0xa4>;
			};

			endpoint@4 {
				reg = <0x04>;
				remote-endpoint = <0x92>;
				phandle = <0x2e>;
			};
		};
	};

	iommu@ff8f3f00 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff8f3f00 0x00 0x100>;
		interrupts = <0x00 0x77 0x04 0x00>;
		interrupt-names = "vopl_mmu";
		clocks = <0x08 0xdb 0x08 0x1db>;
		clock-names = "aclk\0iface";
		power-domains = <0x16 0x12>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0x8d>;
	};

	vop@ff900000 {
		compatible = "rockchip,rk3399-vop-big";
		reg = <0x00 0xff900000 0x00 0x3efc>;
		interrupts = <0x00 0x76 0x04 0x00>;
		assigned-clocks = <0x08 0xd9 0x08 0x1d9>;
		assigned-clock-rates = <0x17d78400 0x5f5e100>;
		clocks = <0x08 0xd9 0x08 0xb4 0x08 0x1d9>;
		clock-names = "aclk_vop\0dclk_vop\0hclk_vop";
		iommus = <0x93>;
		power-domains = <0x16 0x11>;
		resets = <0x08 0x112 0x08 0x116 0x08 0x118>;
		reset-names = "axi\0ahb\0dclk";
		status = "okay";
		u-boot,dm-pre-reloc;

		port {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			phandle = <0x10>;

			endpoint@0 {
				reg = <0x00>;
				remote-endpoint = <0x94>;
				phandle = <0xa6>;
			};

			endpoint@1 {
				reg = <0x01>;
				remote-endpoint = <0x95>;
				phandle = <0xa1>;
			};

			endpoint@2 {
				reg = <0x02>;
				remote-endpoint = <0x96>;
				phandle = <0x9f>;
			};

			endpoint@3 {
				reg = <0x03>;
				remote-endpoint = <0x97>;
				phandle = <0xa3>;
			};

			endpoint@4 {
				reg = <0x04>;
				remote-endpoint = <0x98>;
				phandle = <0x2d>;
			};
		};
	};

	iommu@ff903f00 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff903f00 0x00 0x100>;
		interrupts = <0x00 0x76 0x04 0x00>;
		interrupt-names = "vopb_mmu";
		clocks = <0x08 0xd9 0x08 0x1d9>;
		clock-names = "aclk\0iface";
		power-domains = <0x16 0x11>;
		#iommu-cells = <0x00>;
		status = "okay";
		phandle = <0x93>;
	};

	isp0@ff910000 {
		compatible = "rockchip,rk3399-cif-isp";
		reg = <0x00 0xff910000 0x00 0x4000>;
		interrupts = <0x00 0x2b 0x04 0x00>;
		clocks = <0x08 0x6e 0x08 0xe9 0x08 0x1e3>;
		clock-names = "isp\0aclk\0hclk";
		iommus = <0x99>;
		phys = <0x9a>;
		phy-names = "dphy";
		power-domains = <0x16 0x13>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
			};
		};
	};

	iommu@ff914000 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff914000 0x00 0x100 0x00 0xff915000 0x00 0x100>;
		interrupts = <0x00 0x2b 0x04 0x00>;
		interrupt-names = "isp0_mmu";
		clocks = <0x08 0xe9 0x08 0x1e3>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		power-domains = <0x16 0x13>;
		rockchip,disable-mmu-reset;
		phandle = <0x99>;
	};

	iommu@ff924000 {
		compatible = "rockchip,iommu";
		reg = <0x00 0xff924000 0x00 0x100 0x00 0xff925000 0x00 0x100>;
		interrupts = <0x00 0x2c 0x04 0x00>;
		interrupt-names = "isp1_mmu";
		clocks = <0x08 0xea 0x08 0x1e4>;
		clock-names = "aclk\0iface";
		#iommu-cells = <0x00>;
		power-domains = <0x16 0x14>;
		rockchip,disable-mmu-reset;
	};

	hdmi-sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,mclk-fs = <0x100>;
		simple-audio-card,name = "hdmi-sound";
		status = "okay";

		simple-audio-card,cpu {
			sound-dai = <0x9b>;
		};

		simple-audio-card,codec {
			sound-dai = <0x9c>;
		};
	};

	hdmi@ff940000 {
		compatible = "rockchip,rk3399-dw-hdmi";
		reg = <0x00 0xff940000 0x00 0x20000>;
		interrupts = <0x00 0x17 0x04 0x00>;
		clocks = <0x08 0x174 0x08 0x71 0x08 0x07 0x08 0x16f 0x08 0x70>;
		clock-names = "iahb\0isfr\0vpll\0grf\0cec";
		power-domains = <0x16 0x15>;
		reg-io-width = <0x04>;
		rockchip,grf = <0x17>;
		#sound-dai-cells = <0x00>;
		status = "okay";
		ddc-i2c-bus = <0x9d>;
		pinctrl-names = "default";
		pinctrl-0 = <0x9e>;
		phandle = <0x9c>;

		ports {

			port {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0x9f>;
					phandle = <0x96>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xa0>;
					phandle = <0x90>;
				};
			};
		};
	};

	mipi@ff960000 {
		compatible = "rockchip,rk3399-mipi-dsi\0snps,dw-mipi-dsi";
		reg = <0x00 0xff960000 0x00 0x8000>;
		interrupts = <0x00 0x2d 0x04 0x00>;
		clocks = <0x08 0xa2 0x08 0x170 0x08 0xa3 0x08 0x16f>;
		clock-names = "ref\0pclk\0phy_cfg\0grf";
		power-domains = <0x16 0x0f>;
		resets = <0x08 0xfb>;
		reset-names = "apb";
		rockchip,grf = <0x17>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xa1>;
					phandle = <0x95>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xa2>;
					phandle = <0x8e>;
				};
			};
		};
	};

	mipi@ff968000 {
		compatible = "rockchip,rk3399-mipi-dsi\0snps,dw-mipi-dsi";
		reg = <0x00 0xff968000 0x00 0x8000>;
		interrupts = <0x00 0x2e 0x04 0x00>;
		clocks = <0x08 0xa2 0x08 0x171 0x08 0xa4 0x08 0x16f>;
		clock-names = "ref\0pclk\0phy_cfg\0grf";
		power-domains = <0x16 0x0f>;
		resets = <0x08 0xfc>;
		reset-names = "apb";
		rockchip,grf = <0x17>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xa3>;
					phandle = <0x97>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xa4>;
					phandle = <0x91>;
				};
			};
		};
	};

	edp@ff970000 {
		compatible = "rockchip,rk3399-edp";
		reg = <0x00 0xff970000 0x00 0x8000>;
		interrupts = <0x00 0x0a 0x04 0x00>;
		clocks = <0x08 0x16a 0x08 0x16c 0x08 0x16f>;
		clock-names = "dp\0pclk\0grf";
		pinctrl-names = "default";
		pinctrl-0 = <0xa5>;
		power-domains = <0x16 0x19>;
		resets = <0x08 0x11d>;
		reset-names = "dp";
		rockchip,grf = <0x17>;
		status = "disabled";

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				endpoint@0 {
					reg = <0x00>;
					remote-endpoint = <0xa6>;
					phandle = <0x94>;
				};

				endpoint@1 {
					reg = <0x01>;
					remote-endpoint = <0xa7>;
					phandle = <0x8f>;
				};
			};
		};
	};

	gpu@ff9a0000 {
		compatible = "rockchip,rk3399-mali\0arm,mali-t860";
		reg = <0x00 0xff9a0000 0x00 0x10000>;
		interrupts = <0x00 0x14 0x04 0x00 0x00 0x15 0x04 0x00 0x00 0x13 0x04 0x00>;
		interrupt-names = "job\0mmu\0gpu";
		clocks = <0x08 0xd0>;
		#cooling-cells = <0x02>;
		power-domains = <0x16 0x23>;
		status = "okay";
		operating-points-v2 = <0xa8>;
		mali-supply = <0xa9>;
		phandle = <0x58>;
	};

	pinctrl {
		compatible = "rockchip,rk3399-pinctrl";
		rockchip,grf = <0x17>;
		rockchip,pmu = <0x86>;
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;
		u-boot,dm-pre-reloc;

		gpio0@ff720000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xff720000 0x00 0x100>;
			clocks = <0x71 0x17>;
			interrupts = <0x00 0x0e 0x04 0x00>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x1c>;
		};

		gpio1@ff730000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xff730000 0x00 0x100>;
			clocks = <0x71 0x18>;
			interrupts = <0x00 0x0f 0x04 0x00>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x36>;
		};

		gpio2@ff780000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xff780000 0x00 0x100>;
			clocks = <0x08 0x150>;
			interrupts = <0x00 0x10 0x04 0x00>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0xb7>;
		};

		gpio3@ff788000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xff788000 0x00 0x100>;
			clocks = <0x08 0x151>;
			interrupts = <0x00 0x11 0x04 0x00>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0x1b>;
		};

		gpio4@ff790000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x00 0xff790000 0x00 0x100>;
			clocks = <0x08 0x152>;
			interrupts = <0x00 0x12 0x04 0x00>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			phandle = <0xbc>;
		};

		pcfg-pull-up {
			bias-pull-up;
			phandle = <0xad>;
		};

		pcfg-pull-down {
			bias-pull-down;
			phandle = <0xae>;
		};

		pcfg-pull-none {
			bias-disable;
			phandle = <0xaa>;
		};

		pcfg-pull-none-12ma {
			bias-disable;
			drive-strength = <0x0c>;
			phandle = <0xac>;
		};

		pcfg-pull-none-13ma {
			bias-disable;
			drive-strength = <0x0d>;
			phandle = <0xab>;
		};

		pcfg-pull-none-18ma {
			bias-disable;
			drive-strength = <0x12>;
		};

		pcfg-pull-none-20ma {
			bias-disable;
			drive-strength = <0x14>;
		};

		pcfg-pull-up-2ma {
			bias-pull-up;
			drive-strength = <0x02>;
		};

		pcfg-pull-up-8ma {
			bias-pull-up;
			drive-strength = <0x08>;
		};

		pcfg-pull-up-18ma {
			bias-pull-up;
			drive-strength = <0x12>;
		};

		pcfg-pull-up-20ma {
			bias-pull-up;
			drive-strength = <0x14>;
		};

		pcfg-pull-down-4ma {
			bias-pull-down;
			drive-strength = <0x04>;
		};

		pcfg-pull-down-8ma {
			bias-pull-down;
			drive-strength = <0x08>;
		};

		pcfg-pull-down-12ma {
			bias-pull-down;
			drive-strength = <0x0c>;
		};

		pcfg-pull-down-18ma {
			bias-pull-down;
			drive-strength = <0x12>;
		};

		pcfg-pull-down-20ma {
			bias-pull-down;
			drive-strength = <0x14>;
		};

		pcfg-output-high {
			output-high;
			phandle = <0xaf>;
		};

		pcfg-output-low {
			output-low;
		};

		clock {

			clk-32k {
				rockchip,pins = <0x00 0x00 0x02 0xaa>;
			};
		};

		edp {

			edp-hpd {
				rockchip,pins = <0x04 0x17 0x02 0xaa>;
				phandle = <0xa5>;
			};
		};

		gmac {

			rgmii-pins {
				rockchip,pins = <0x03 0x11 0x01 0xab 0x03 0x0e 0x01 0xaa 0x03 0x0d 0x01 0xaa 0x03 0x0c 0x01 0xab 0x03 0x0b 0x01 0xaa 0x03 0x09 0x01 0xaa 0x03 0x08 0x01 0xaa 0x03 0x07 0x01 0xaa 0x03 0x06 0x01 0xaa 0x03 0x05 0x01 0xab 0x03 0x04 0x01 0xab 0x03 0x03 0x01 0xaa 0x03 0x02 0x01 0xaa 0x03 0x01 0x01 0xab 0x03 0x00 0x01 0xab>;
				phandle = <0x1a>;
			};

			rmii-pins {
				rockchip,pins = <0x03 0x0d 0x01 0xaa 0x03 0x0c 0x01 0xab 0x03 0x0b 0x01 0xaa 0x03 0x0a 0x01 0xaa 0x03 0x09 0x01 0xaa 0x03 0x08 0x01 0xaa 0x03 0x07 0x01 0xaa 0x03 0x06 0x01 0xaa 0x03 0x05 0x01 0xab 0x03 0x04 0x01 0xab>;
			};
		};

		i2c0 {

			i2c0-xfer {
				rockchip,pins = <0x01 0x0f 0x02 0xaa 0x01 0x10 0x02 0xaa>;
				phandle = <0x77>;
			};
		};

		i2c1 {

			i2c1-xfer {
				rockchip,pins = <0x04 0x02 0x01 0xaa 0x04 0x01 0x01 0xaa>;
				phandle = <0x30>;
			};
		};

		i2c2 {

			i2c2-xfer {
				rockchip,pins = <0x02 0x01 0x02 0xac 0x02 0x00 0x02 0xac>;
				phandle = <0x31>;
			};
		};

		i2c3 {

			i2c3-xfer {
				rockchip,pins = <0x04 0x11 0x01 0xaa 0x04 0x10 0x01 0xaa>;
				phandle = <0x32>;
			};
		};

		i2c4 {

			i2c4-xfer {
				rockchip,pins = <0x01 0x0c 0x01 0xaa 0x01 0x0b 0x01 0xaa>;
				phandle = <0x7c>;
			};
		};

		i2c5 {

			i2c5-xfer {
				rockchip,pins = <0x03 0x0b 0x02 0xaa 0x03 0x0a 0x02 0xaa>;
				phandle = <0x33>;
			};
		};

		i2c6 {

			i2c6-xfer {
				rockchip,pins = <0x02 0x0a 0x02 0xaa 0x02 0x09 0x02 0xaa>;
				phandle = <0x34>;
			};
		};

		i2c7 {

			i2c7-xfer {
				rockchip,pins = <0x02 0x08 0x02 0xaa 0x02 0x07 0x02 0xaa>;
				phandle = <0x35>;
			};
		};

		i2c8 {

			i2c8-xfer {
				rockchip,pins = <0x01 0x15 0x01 0xaa 0x01 0x14 0x01 0xaa>;
				phandle = <0x7f>;
			};
		};

		i2s0 {

			i2s0-2ch-bus {
				rockchip,pins = <0x03 0x18 0x01 0xaa 0x03 0x19 0x01 0xaa 0x03 0x1a 0x01 0xaa 0x03 0x1b 0x01 0xaa 0x03 0x1f 0x01 0xaa 0x04 0x00 0x01 0xaa>;
			};

			i2s0-8ch-bus {
				rockchip,pins = <0x03 0x18 0x01 0xaa 0x03 0x19 0x01 0xaa 0x03 0x1a 0x01 0xaa 0x03 0x1b 0x01 0xaa 0x03 0x1c 0x01 0xaa 0x03 0x1d 0x01 0xaa 0x03 0x1e 0x01 0xaa 0x03 0x1f 0x01 0xaa 0x04 0x00 0x01 0xaa>;
				phandle = <0x8b>;
			};
		};

		i2s1 {

			i2s1-2ch-bus {
				rockchip,pins = <0x04 0x03 0x01 0xaa 0x04 0x04 0x01 0xaa 0x04 0x05 0x01 0xaa 0x04 0x06 0x01 0xaa 0x04 0x07 0x01 0xaa>;
				phandle = <0x8c>;
			};
		};

		sdio0 {

			sdio0-bus1 {
				rockchip,pins = <0x02 0x14 0x01 0xad>;
			};

			sdio0-bus4 {
				rockchip,pins = <0x02 0x14 0x01 0xad 0x02 0x15 0x01 0xad 0x02 0x16 0x01 0xad 0x02 0x17 0x01 0xad>;
			};

			sdio0-cmd {
				rockchip,pins = <0x02 0x18 0x01 0xad>;
			};

			sdio0-clk {
				rockchip,pins = <0x02 0x19 0x01 0xaa>;
			};

			sdio0-cd {
				rockchip,pins = <0x02 0x1a 0x01 0xad>;
			};

			sdio0-pwr {
				rockchip,pins = <0x02 0x1b 0x01 0xad>;
			};

			sdio0-bkpwr {
				rockchip,pins = <0x02 0x1c 0x01 0xad>;
			};

			sdio0-wp {
				rockchip,pins = <0x00 0x03 0x01 0xad>;
			};

			sdio0-int {
				rockchip,pins = <0x00 0x04 0x01 0xad>;
			};
		};

		sdmmc {

			sdmmc-bus1 {
				rockchip,pins = <0x04 0x08 0x01 0xad>;
			};

			sdmmc-bus4 {
				rockchip,pins = <0x04 0x08 0x01 0xad 0x04 0x09 0x01 0xad 0x04 0x0a 0x01 0xad 0x04 0x0b 0x01 0xad>;
				phandle = <0x1f>;
			};

			sdmmc-clk {
				rockchip,pins = <0x04 0x0c 0x01 0xaa>;
				phandle = <0x1d>;
			};

			sdmmc-cmd {
				rockchip,pins = <0x04 0x0d 0x01 0xad>;
				phandle = <0x1e>;
			};

			sdmmc-cd {
				rockchip,pins = <0x00 0x07 0x01 0xad>;
			};

			sdmmc-wp {
				rockchip,pins = <0x00 0x08 0x01 0xad>;
			};

			vcc3v0-sd-en {
				rockchip,pins = <0x04 0x1e 0x00 0xaa>;
				phandle = <0xbd>;
			};
		};

		suspend {

			ap-pwroff {
				rockchip,pins = <0x01 0x05 0x01 0xaa>;
			};

			ddrio-pwroff {
				rockchip,pins = <0x00 0x01 0x01 0xaa>;
			};
		};

		spdif {

			spdif-bus {
				rockchip,pins = <0x04 0x15 0x01 0xaa>;
				phandle = <0x8a>;
			};

			spdif-bus-1 {
				rockchip,pins = <0x03 0x10 0x03 0xaa>;
			};
		};

		spi0 {

			spi0-clk {
				rockchip,pins = <0x03 0x06 0x02 0xad>;
				phandle = <0x3f>;
			};

			spi0-cs0 {
				rockchip,pins = <0x03 0x07 0x02 0xad>;
				phandle = <0x42>;
			};

			spi0-cs1 {
				rockchip,pins = <0x03 0x08 0x02 0xad>;
			};

			spi0-tx {
				rockchip,pins = <0x03 0x05 0x02 0xad>;
				phandle = <0x40>;
			};

			spi0-rx {
				rockchip,pins = <0x03 0x04 0x02 0xad>;
				phandle = <0x41>;
			};
		};

		spi1 {

			spi1-clk {
				rockchip,pins = <0x01 0x09 0x02 0xad>;
				phandle = <0x43>;
			};

			spi1-cs0 {
				rockchip,pins = <0x01 0x0a 0x02 0xad>;
				phandle = <0x46>;
			};

			spi1-rx {
				rockchip,pins = <0x01 0x07 0x02 0xad>;
				phandle = <0x45>;
			};

			spi1-tx {
				rockchip,pins = <0x01 0x08 0x02 0xad>;
				phandle = <0x44>;
			};
		};

		spi2 {

			spi2-clk {
				rockchip,pins = <0x02 0x0b 0x01 0xad>;
				phandle = <0x47>;
			};

			spi2-cs0 {
				rockchip,pins = <0x02 0x0c 0x01 0xad>;
				phandle = <0x4a>;
			};

			spi2-rx {
				rockchip,pins = <0x02 0x09 0x01 0xad>;
				phandle = <0x49>;
			};

			spi2-tx {
				rockchip,pins = <0x02 0x0a 0x01 0xad>;
				phandle = <0x48>;
			};
		};

		spi3 {

			spi3-clk {
				rockchip,pins = <0x01 0x11 0x01 0xad>;
				phandle = <0x72>;
			};

			spi3-cs0 {
				rockchip,pins = <0x01 0x12 0x01 0xad>;
				phandle = <0x75>;
			};

			spi3-rx {
				rockchip,pins = <0x01 0x0f 0x01 0xad>;
				phandle = <0x74>;
			};

			spi3-tx {
				rockchip,pins = <0x01 0x10 0x01 0xad>;
				phandle = <0x73>;
			};
		};

		spi4 {

			spi4-clk {
				rockchip,pins = <0x03 0x02 0x02 0xad>;
				phandle = <0x4b>;
			};

			spi4-cs0 {
				rockchip,pins = <0x03 0x03 0x02 0xad>;
				phandle = <0x4e>;
			};

			spi4-rx {
				rockchip,pins = <0x03 0x00 0x02 0xad>;
				phandle = <0x4d>;
			};

			spi4-tx {
				rockchip,pins = <0x03 0x01 0x02 0xad>;
				phandle = <0x4c>;
			};
		};

		spi5 {

			spi5-clk {
				rockchip,pins = <0x02 0x16 0x02 0xad>;
				phandle = <0x50>;
			};

			spi5-cs0 {
				rockchip,pins = <0x02 0x17 0x02 0xad>;
				phandle = <0x53>;
			};

			spi5-rx {
				rockchip,pins = <0x02 0x14 0x02 0xad>;
				phandle = <0x52>;
			};

			spi5-tx {
				rockchip,pins = <0x02 0x15 0x02 0xad>;
				phandle = <0x51>;
			};
		};

		testclk {

			test-clkout0 {
				rockchip,pins = <0x00 0x00 0x01 0xaa>;
			};

			test-clkout1 {
				rockchip,pins = <0x02 0x19 0x02 0xaa>;
			};

			test-clkout2 {
				rockchip,pins = <0x00 0x08 0x03 0xaa>;
			};
		};

		tsadc {

			otp-pin {
				rockchip,pins = <0x01 0x06 0x00 0xaa>;
				phandle = <0x59>;
			};

			otp-out {
				rockchip,pins = <0x01 0x06 0x01 0xaa>;
				phandle = <0x5a>;
			};
		};

		uart0 {

			uart0-xfer {
				rockchip,pins = <0x02 0x10 0x01 0xad 0x02 0x11 0x01 0xaa>;
				phandle = <0x39>;
			};

			uart0-cts {
				rockchip,pins = <0x02 0x12 0x01 0xaa>;
				phandle = <0x3a>;
			};

			uart0-rts {
				rockchip,pins = <0x02 0x13 0x01 0xaa>;
			};
		};

		uart1 {

			uart1-xfer {
				rockchip,pins = <0x03 0x0c 0x02 0xad 0x03 0x0d 0x02 0xaa>;
				phandle = <0x3b>;
			};
		};

		uart2a {

			uart2a-xfer {
				rockchip,pins = <0x04 0x08 0x02 0xad 0x04 0x09 0x02 0xaa>;
			};
		};

		uart2b {

			uart2b-xfer {
				rockchip,pins = <0x04 0x10 0x02 0xad 0x04 0x11 0x02 0xaa>;
			};
		};

		uart2c {

			uart2c-xfer {
				rockchip,pins = <0x04 0x13 0x01 0xad 0x04 0x14 0x01 0xaa>;
				phandle = <0x3c>;
			};
		};

		uart3 {

			uart3-xfer {
				rockchip,pins = <0x03 0x0e 0x02 0xad 0x03 0x0f 0x02 0xaa>;
				phandle = <0x3d>;
			};

			uart3-cts {
				rockchip,pins = <0x03 0x10 0x02 0xaa>;
			};

			uart3-rts {
				rockchip,pins = <0x03 0x11 0x02 0xaa>;
			};
		};

		uart4 {

			uart4-xfer {
				rockchip,pins = <0x01 0x07 0x01 0xad 0x01 0x08 0x01 0xaa>;
				phandle = <0x76>;
			};
		};

		uarthdcp {

			uarthdcp-xfer {
				rockchip,pins = <0x04 0x15 0x02 0xad 0x04 0x16 0x02 0xaa>;
			};
		};

		pwm0 {

			pwm0-pin {
				rockchip,pins = <0x04 0x12 0x01 0xaa>;
				phandle = <0x80>;
			};

			pwm0-pin-pull-down {
				rockchip,pins = <0x04 0x12 0x01 0xae>;
			};

			vop0-pwm-pin {
				rockchip,pins = <0x04 0x12 0x02 0xaa>;
			};

			vop1-pwm-pin {
				rockchip,pins = <0x04 0x12 0x03 0xaa>;
			};
		};

		pwm1 {

			pwm1-pin {
				rockchip,pins = <0x04 0x16 0x01 0xaa>;
				phandle = <0x81>;
			};

			pwm1-pin-pull-down {
				rockchip,pins = <0x04 0x16 0x01 0xae>;
			};
		};

		pwm2 {

			pwm2-pin {
				rockchip,pins = <0x01 0x13 0x01 0xaa>;
				phandle = <0x82>;
			};

			pwm2-pin-pull-down {
				rockchip,pins = <0x01 0x13 0x01 0xae>;
			};
		};

		pwm3a {

			pwm3a-pin {
				rockchip,pins = <0x00 0x06 0x01 0xaa>;
				phandle = <0x83>;
			};
		};

		pwm3b {

			pwm3b-pin {
				rockchip,pins = <0x01 0x0e 0x01 0xaa>;
			};
		};

		hdmi {

			hdmi-i2c-xfer {
				rockchip,pins = <0x04 0x11 0x03 0xaa 0x04 0x10 0x03 0xaa>;
			};

			hdmi-cec {
				rockchip,pins = <0x04 0x17 0x01 0xaa>;
				phandle = <0x9e>;
			};
		};

		pcie {

			pci-clkreqn-cpm {
				rockchip,pins = <0x02 0x1a 0x00 0xaa>;
			};

			pci-clkreqnb-cpm {
				rockchip,pins = <0x04 0x18 0x00 0xaa>;
			};
		};

		buttons {

			pwr-key-l {
				rockchip,pins = <0x00 0x05 0x00 0xad>;
				phandle = <0xb2>;
			};
		};

		ir {

			ir-int {
				rockchip,pins = <0x00 0x06 0x00 0xaa>;
				phandle = <0xb3>;
			};
		};

		lcd-panel {

			lcd-panel-reset {
				rockchip,pins = <0x04 0x1d 0x00 0xad>;
			};
		};

		leds {

			diy-led-pin {
				rockchip,pins = <0x00 0x0d 0x00 0xaa>;
				phandle = <0xb5>;
			};

			work-led-pin {
				rockchip,pins = <0x02 0x1b 0x00 0xaa>;
				phandle = <0xb4>;
			};

			yellow-led-pin {
				rockchip,pins = <0x00 0x02 0x00 0xaa>;
				phandle = <0xb6>;
			};
		};

		pmic {

			vsel1-pin {
				rockchip,pins = <0x01 0x12 0x00 0xae>;
				phandle = <0x7a>;
			};

			vsel2-pin {
				rockchip,pins = <0x01 0x0e 0x00 0xae>;
				phandle = <0x7b>;
			};

			pmic-int-l {
				rockchip,pins = <0x01 0x15 0x00 0xad>;
				phandle = <0x78>;
			};
		};

		sdio-pwrseq {

			wifi-enable-h {
				rockchip,pins = <0x00 0x0a 0x00 0xaa>;
				phandle = <0xb9>;
			};
		};

		usb2 {

			vcc5v0-host-en {
				rockchip,pins = <0x01 0x00 0x00 0xaa>;
				phandle = <0xbf>;
			};

			vcc-sys-en {
				rockchip,pins = <0x02 0x06 0x00 0xaa>;
				phandle = <0xc3>;
			};

			hub-rst {
				rockchip,pins = <0x02 0x04 0x00 0xaf>;
				phandle = <0xc0>;
			};
		};

		usb-typec {

			vcc-vbus-typec1-en {
				rockchip,pins = <0x01 0x0d 0x00 0xaa>;
				phandle = <0xc2>;
			};
		};

		fusb30x {

			fusb0-int {
				rockchip,pins = <0x01 0x02 0x00 0xad>;
				phandle = <0x37>;
			};

			fusb1-int {
				rockchip,pins = <0x01 0x01 0x00 0xad>;
				phandle = <0x7d>;
			};
		};
	};

	opp-table0 {
		compatible = "operating-points-v2";
		opp-shared;
		phandle = <0x0b>;

		opp00 {
			opp-hz = <0x00 0x18519600>;
			opp-microvolt = <0xc96a8 0xc96a8 0x1312d0>;
			clock-latency-ns = <0x9c40>;
		};

		opp01 {
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xc96a8 0xc96a8 0x1312d0>;
		};

		opp02 {
			opp-hz = <0x00 0x30a32c00>;
			opp-microvolt = <0xcf850 0xcf850 0x1312d0>;
		};

		opp03 {
			opp-hz = <0x00 0x3c14dc00>;
			opp-microvolt = <0xe1d48 0xe1d48 0x1312d0>;
		};

		opp04 {
			opp-hz = <0x00 0x47868c00>;
			opp-microvolt = <0xf4240 0xf4240 0x1312d0>;
		};

		opp05 {
			opp-hz = <0x00 0x54667200>;
			opp-microvolt = <0x112a88 0x112a88 0x1312d0>;
		};
	};

	opp-table1 {
		compatible = "operating-points-v2";
		opp-shared;
		phandle = <0x0d>;

		opp00 {
			opp-hz = <0x00 0x18519600>;
			opp-microvolt = <0xc96a8 0xc96a8 0x1312d0>;
			clock-latency-ns = <0x9c40>;
		};

		opp01 {
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xc96a8 0xc96a8 0x1312d0>;
		};

		opp02 {
			opp-hz = <0x00 0x30a32c00>;
			opp-microvolt = <0xc96a8 0xc96a8 0x1312d0>;
		};

		opp03 {
			opp-hz = <0x00 0x3c14dc00>;
			opp-microvolt = <0xd59f8 0xd59f8 0x1312d0>;
		};

		opp04 {
			opp-hz = <0x00 0x47868c00>;
			opp-microvolt = <0xe7ef0 0xe7ef0 0x1312d0>;
		};

		opp05 {
			opp-hz = <0x00 0x54667200>;
			opp-microvolt = <0xfa3e8 0xfa3e8 0x1312d0>;
		};

		opp06 {
			opp-hz = <0x00 0x5fd82200>;
			opp-microvolt = <0x10c8e0 0x10c8e0 0x1312d0>;
		};

		opp07 {
			opp-hz = <0x00 0x6b49d200>;
			opp-microvolt = <0x124f80 0x124f80 0x1312d0>;
		};
	};

	opp-table2 {
		compatible = "operating-points-v2";
		phandle = <0xa8>;

		opp00 {
			opp-hz = <0x00 0xbebc200>;
			opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
		};

		opp01 {
			opp-hz = <0x00 0x11b3dc40>;
			opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
		};

		opp02 {
			opp-hz = <0x00 0x17d78400>;
			opp-microvolt = <0xc96a8 0xc96a8 0x118c30>;
		};

		opp03 {
			opp-hz = <0x00 0x1dcd6500>;
			opp-microvolt = <0xd59f8 0xd59f8 0x118c30>;
		};

		opp04 {
			opp-hz = <0x00 0x23c34600>;
			opp-microvolt = <0xe1d48 0xe1d48 0x118c30>;
		};

		opp05 {
			opp-hz = <0x00 0x2faf0800>;
			opp-microvolt = <0x10c8e0 0x10c8e0 0x118c30>;
		};
	};

	chosen {
		stdout-path = "serial2:1500000n8";
		u-boot,spl-boot-order = "same-as-spl\0/spi@ff1d0000/flash@0\0/mmc@fe330000\0/mmc@fe320000";
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <0xb0 0x00 0x61a8 0x00>;
	};

	external-gmac-clock {
		compatible = "fixed-clock";
		clock-frequency = <0x7735940>;
		clock-output-names = "clkin_gmac";
		#clock-cells = <0x00>;
		phandle = <0x18>;
	};

	adc-keys {
		compatible = "adc-keys";
		io-channels = <0xb1 0x01>;
		io-channel-names = "buttons";
		keyup-threshold-microvolt = <0x16e360>;
		poll-interval = <0x64>;

		recovery {
			label = "Recovery";
			linux,code = <0x168>;
			press-threshold-microvolt = <0x4650>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		pinctrl-names = "default";
		pinctrl-0 = <0xb2>;

		power {
			debounce-interval = <0x64>;
			gpios = <0x1c 0x05 0x01>;
			label = "GPIO Key Power";
			linux,code = <0x74>;
			wakeup-source;
		};
	};

	ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <0x1c 0x06 0x01>;
		pinctrl-names = "default";
		pinctrl-0 = <0xb3>;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <0xb4 0xb5 0xb6>;

		led-0 {
			label = "green:work";
			gpios = <0xb7 0x1b 0x00>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		led-1 {
			label = "red:diy";
			gpios = <0x1c 0x0d 0x00>;
			default-state = "off";
			linux,default-trigger = "mmc2";
		};

		led-2 {
			label = "yellow:yellow-led";
			gpios = <0x1c 0x02 0x00>;
			default-state = "off";
			linux,default-trigger = "mmc1";
		};
	};

	sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <0xb8 0x01>;
		clock-names = "ext_clock";
		pinctrl-names = "default";
		pinctrl-0 = <0xb9>;
		reset-gpios = <0x1c 0x0a 0x01>;
	};

	vcc-vbus-typec0 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_vbus_typec0";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		phandle = <0x38>;
	};

	sys-12v {
		compatible = "regulator-fixed";
		regulator-name = "sys_12v";
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <0xba>;
		phandle = <0xbe>;
	};

	vcc1v8-s3 {
		compatible = "regulator-fixed";
		regulator-name = "vcc1v8_s3";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x1b7740>;
		regulator-max-microvolt = <0x1b7740>;
		vin-supply = <0xbb>;
		phandle = <0x2f>;
	};

	vcc3v0-sd {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0xbc 0x1e 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xbd>;
		regulator-name = "vcc3v0_sd";
		regulator-boot-on;
		regulator-min-microvolt = <0x2dc6c0>;
		regulator-max-microvolt = <0x2dc6c0>;
		vin-supply = <0x79>;
		phandle = <0x20>;
	};

	vcc3v3-sys {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		vin-supply = <0xbe>;
		phandle = <0x79>;
	};

	vcca-0v9 {
		compatible = "regulator-fixed";
		regulator-name = "vcca_0v9";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0xdbba0>;
		regulator-max-microvolt = <0xdbba0>;
		vin-supply = <0x79>;
	};

	vcc5v0-host-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0x36 0x00 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xbf 0xc0>;
		regulator-name = "vcc5v0_host";
		vin-supply = <0xc1>;
		regulator-always-on;
		phandle = <0x88>;
	};

	vcc-vbus-typec1 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0x36 0x0d 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xc2>;
		regulator-name = "vcc_vbus_typec1";
		regulator-always-on;
		vin-supply = <0xc1>;
		phandle = <0x7e>;
	};

	vcc-sys {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0xb7 0x06 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xc3>;
		regulator-name = "vcc_sys";
		regulator-boot-on;
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		vin-supply = <0xbe>;
		regulator-always-on;
		phandle = <0xc1>;
	};

	vdd-log {
		compatible = "pwm-regulator";
		pwms = <0xc4 0x00 0x61a8 0x01>;
		regulator-name = "vdd_log";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x68fb0>;
		regulator-max-microvolt = <0x155cc0>;
		pwm-supply = <0x79>;
		regulator-init-microvolt = <0xe7ef0>;
	};

	binman {
		multiple-images;

		simple-bin {
			filename = "u-boot-rockchip.bin";
			pad-byte = <0xff>;

			mkimage {
				filename = "idbloader.img";
				args = "-n\0rk3399\0-T\0rksd";
				multiple-data-files;

				u-boot-tpl {
				};

				u-boot-spl {
				};
			};

			fit {
				description = "FIT image for U-Boot with bl31 (TF-A)";
				#address-cells = <0x01>;
				fit,fdt-list = "of-list";
				filename = "u-boot.itb";
				fit,external-offset = <0x00>;
				fit,align = <0x200>;
				offset = <0x7f8000>;

				images {

					u-boot {
						description = "U-Boot (64-bit)";
						type = "standalone";
						os = "U-Boot";
						arch = "arm64";
						compression = "none";
						load = <0x200000>;
						entry = <0x200000>;

						u-boot-nodtb {
						};
					};

					@atf-SEQ {
						fit,operation = "split-elf";
						description = "ARM Trusted Firmware";
						type = "firmware";
						arch = "arm64";
						os = "arm-trusted-firmware";
						compression = "none";
						fit,load;
						fit,entry;
						fit,data;

						atf-bl31 {
						};
					};

					@tee-SEQ {
						fit,operation = "split-elf";
						description = "TEE";
						type = "tee";
						arch = "arm64";
						os = "tee";
						compression = "none";
						fit,load;
						fit,entry;
						fit,data;

						tee-os {
							optional;
						};
					};

					@fdt-SEQ {
						description = "fdt-NAME";
						compression = "none";
						type = "flat_dt";
					};
				};

				configurations {
					default = "@config-DEFAULT-SEQ";

					@config-SEQ {
						description = "NAME.dtb";
						fdt = "fdt-SEQ";
						fit,firmware = "atf-1\0u-boot";
						fit,loadables;
					};
				};
			};
		};
	};

	syscon@ff620000 {
		u-boot,dm-pre-reloc;
		compatible = "rockchip,rk3399-cic\0syscon";
		reg = <0x00 0xff620000 0x00 0x100>;
	};

	dfi@ff630000 {
		u-boot,dm-pre-reloc;
		reg = <0x00 0xff630000 0x00 0x4000>;
		compatible = "rockchip,rk3399-dfi";
		rockchip,pmu = <0x86>;
		clocks = <0x08 0x179>;
		clock-names = "pclk_ddr_mon";
		phandle = <0xc5>;
	};

	rng@ff8b8000 {
		compatible = "rockchip,cryptov1-rng";
		reg = <0x00 0xff8b8000 0x00 0x1000>;
		status = "okay";
	};

	dmc {
		u-boot,dm-pre-reloc;
		compatible = "rockchip,rk3399-dmc";
		devfreq-events = <0xc5>;
		interrupts = <0x00 0x01 0x04 0x00>;
		clocks = <0x08 0xaa>;
		clock-names = "dmc_clk";
		reg = <0x00 0xffa80000 0x00 0x800 0x00 0xffa80800 0x00 0x1800 0x00 0xffa82000 0x00 0x2000 0x00 0xffa84000 0x00 0x1000 0x00 0xffa88000 0x00 0x800 0x00 0xffa88800 0x00 0x1800 0x00 0xffa8a000 0x00 0x2000 0x00 0xffa8c000 0x00 0x1000>;
		rockchip,sdram-params = <0x02 0x0a 0x03 0x02 0x01 0x00 0x0f 0x0f 0x0f 0x0f 0x01 0x80241d22 0x15050f08 0x602 0x2122 0x4c 0x00 0x02 0x0a 0x03 0x02 0x01 0x00 0x0f 0x0f 0x0f 0x0f 0x01 0x80241d22 0x15050f08 0x602 0x2122 0x4c 0x00 0x32 0x07 0x02 0x0d 0x01 0xb00 0x00 0x00 0x00 0x00 0x13880 0xc3500 0x05 0x320 0x27100 0x186a00 0x05 0x640 0x2710 0x186a0 0x05 0x1000064 0x00 0x2020101 0x102 0x50 0xc8 0x00 0x6140000 0x81c00 0x400040c 0x19042008 0x10080a11 0x22310800 0x200f0a 0xa030704 0x8000204 0xa0a 0x4006db0 0xa0a0804 0x600db60 0xa0a0806 0x4000db6 0x2030404 0xf0a0800 0x8040411 0x1400640a 0x2010a0a 0x10001 0x4082012 0x41109 0x00 0x3010000 0x6100048 0xc280090 0xbb0009 0x00 0x60005 0xa0005 0xa0014 0x1000000 0x30a0000 0xc000002 0x103 0x5030a 0x60037 0x5006e 0x5050007 0x3030605 0x6050301 0x6030c05 0x5050302 0x3030305 0x301 0x301 0x01 0x00 0x00 0x1000000 0x80104002 0x40003 0x40005 0x30000 0x50004 0x04 0x40003 0x40005 0x18400000 0xc20 0x185030a0 0x2ec0000 0x176 0x00 0x00 0x00 0x00 0x00 0x6030300 0x30303 0x2030200 0x40703 0x3020302 0x2000407 0x7030203 0x30f04 0x70004 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x10000 0x20040020 0x200400 0x1000400 0xb80 0x00 0x01 0x02 0x0e 0x00 0x00 0x00 0x00 0x00 0x500000 0x640028 0x640404 0x5000a0 0x60600c8 0xa00c8 0xd0005 0xd0404 0x00 0x00 0x00 0x1400a3 0xe30009 0x120024 0x40063 0x00 0x310031 0x31 0x4d0000 0x4d004d 0x4d0000 0x4d004d 0x10101 0x00 0x00 0x1400a3 0xe30009 0x120024 0x40063 0x00 0x310031 0x31 0x4d0000 0x4d004d 0x4d0000 0x4d004d 0x10101 0x00 0x00 0x00 0x01 0x00 0x18151100 0x0c 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x20003 0x400100 0xc0190 0x1000200 0x3200040 0x20018 0x400100 0x80032 0x140000 0x30028 0x1010100 0x2000202 0xb000002 0x1000f0f 0x00 0x00 0x10003 0xc03 0x40101 0x4010100 0x1000000 0x2010000 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x10000 0x01 0x1010001 0x5040001 0x40a0703 0x2080808 0x20e000a 0x20f010b 0xd0008 0x80b0a 0x3000200 0x100 0x00 0x00 0xd000001 0x28 0x10000 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x10100 0x1000000 0x01 0x303 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x556aa 0xaaaaa 0xaa955 0x55555 0xb3133 0x4cd33 0x4cecc 0xb32cc 0x10300 0x3000100 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xffff00 0x1a160000 0x8000012 0xc20 0x200 0x200 0x200 0x200 0xc20 0x7940 0x18500409 0x200 0x200 0x200 0x200 0x1850 0xf320 0x176060c 0x200 0x200 0x200 0x200 0x176 0xe9c 0x2020205 0x3030202 0x18 0x00 0x00 0x1403 0x00 0x00 0x00 0x30000 0xa001c 0xe0020 0x60018 0x00 0x00 0x2000000 0x90305 0x50101 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1000001 0x1010101 0x1000101 0x1000100 0x10001 0x10002 0x20100 0x02 0xb00 0x00 0x2ec 0x176 0x30a0 0x1850 0x1840 0x1760c20 0x200 0x200 0x200 0x200 0x1850 0x200 0x200 0x200 0x200 0xc20 0x200 0x200 0x200 0x200 0x10000 0x07 0x1000001 0x00 0x3fffffff 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xf000101 0x82b3223 0x80c0004 0x61c00 0x214 0xbb0009 0xc280090 0x6100048 0x500 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4040100 0xa000004 0x128 0x00 0x3000f 0x18 0x00 0x00 0x60002 0x10001 0x101 0x20001 0x80004 0x00 0x5030000 0x70a0404 0x00 0x00 0x00 0xf0f00 0x1e 0x00 0x1010300 0x00 0x00 0x1000000 0x101 0x55555a5a 0x55555a5a 0x55555a5a 0x55555a5a 0xc050001 0x6020009 0x10004 0x203 0x30000 0x170f0000 0x60018 0xe0020 0xa001c 0x00 0x00 0x100 0x140a0000 0xd010a 0x100c802 0x10a0064 0xe0100 0x100000e 0xc900c9 0x650100 0x1e1a0065 0x10010204 0x6070605 0x20000202 0x201000 0x201000 0x4041000 0x10020100 0x3010c 0x4b004a 0x1a0f0000 0x102041e 0x34000000 0x00 0x00 0x10000 0x400 0x310000 0x4d4d00 0x120024 0x4d000031 0x144d 0x310009 0x4d4d00 0x04 0x4d000031 0x244d 0x310012 0x4d4d00 0x90014 0x4d000031 0x4004d 0x310000 0x4d4d00 0x120024 0x4d000031 0x144d 0x310009 0x4d4d00 0x04 0x4d000031 0x244d 0x310012 0x4d4d00 0x90014 0x4d000031 0x200004d 0xc8000d 0x8080064 0x40a0404 0x3000d92 0x10a2001 0xf11080a 0x110a 0x2200d92e 0x80c2003 0x809080a 0xa0a 0x11006c97 0x40a2002 0x200020a 0x2000200 0x2000200 0x2000200 0x2000200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1000400 0x17600 0xe9c 0x1850 0xf320 0xc20 0x7940 0x8000000 0x100 0x00 0x00 0x00 0x00 0x02 0x76543210 0x4f008 0x20159 0x00 0x00 0x10000 0x1665555 0x3665555 0x10f00 0x4000100 0x00 0x170180 0xcc0201 0x30066 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4080000 0x4080400 0x30000000 0xc00c007 0x100 0x00 0xfd02fe01 0xf708fb04 0xdf20ef10 0x7f80bf40 0x1aaaa 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x200000 0x00 0x00 0x00 0x00 0x00 0x00 0x2800280 0x2800280 0x2800280 0x2800280 0x280 0x00 0x00 0x00 0x00 0x800000 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x1590080 0x00 0x00 0x00 0x200 0x00 0x51315152 0xc0003150 0x10000c0 0x100c00 0x7044204 0xf0c18 0x1000140 0xc10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x76543210 0x4f008 0x20159 0x00 0x00 0x10000 0x1665555 0x3665555 0x10f00 0x4000100 0x00 0x170180 0xcc0201 0x30066 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4080000 0x4080400 0x30000000 0xc00c007 0x100 0x00 0xfd02fe01 0xf708fb04 0xdf20ef10 0x7f80bf40 0xaaaa 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x200000 0x00 0x00 0x00 0x00 0x00 0x00 0x2800280 0x2800280 0x2800280 0x2800280 0x280 0x00 0x00 0x00 0x00 0x800000 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x1590080 0x00 0x00 0x00 0x200 0x00 0x51315152 0xc0003150 0x10000c0 0x100c00 0x7044204 0xf0c18 0x1000140 0xc10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x76543210 0x4f008 0x20159 0x00 0x00 0x10000 0x1665555 0x3665555 0x10f00 0x4000100 0x00 0x170180 0xcc0201 0x30066 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4080000 0x4080400 0x30000000 0xc00c007 0x100 0x00 0xfd02fe01 0xf708fb04 0xdf20ef10 0x7f80bf40 0x1aaaa 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x200000 0x00 0x00 0x00 0x00 0x00 0x00 0x2800280 0x2800280 0x2800280 0x2800280 0x280 0x00 0x00 0x00 0x00 0x800000 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x1590080 0x00 0x00 0x00 0x200 0x00 0x51315152 0xc0003150 0x10000c0 0x100c00 0x7044204 0xf0c18 0x1000140 0xc10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x76543210 0x4f008 0x20159 0x00 0x00 0x10000 0x1665555 0x3665555 0x10f00 0x4000100 0x00 0x170180 0xcc0201 0x30066 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4080000 0x4080400 0x30000000 0xc00c007 0x100 0x00 0xfd02fe01 0xf708fb04 0xdf20ef10 0x7f80bf40 0xaaaa 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x200000 0x00 0x00 0x00 0x00 0x00 0x00 0x2800280 0x2800280 0x2800280 0x2800280 0x280 0x00 0x00 0x00 0x00 0x800000 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x800080 0x1590080 0x00 0x00 0x00 0x200 0x00 0x51315152 0xc0003150 0x10000c0 0x100c00 0x7044204 0xf0c18 0x1000140 0xc10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x400320 0x40 0xdcba98 0x00 0xdcba98 0x1000000 0x20003 0x00 0x00 0x00 0x2a 0x15 0x15 0x2a 0x33 0x0c 0x0c 0x33 0xa418820 0x3f0000 0x3f 0x30055 0x3000300 0x3000300 0xc0300 0x42080010 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x400320 0x40 0x00 0x00 0x00 0x1000000 0x20003 0x00 0x00 0x00 0x2a 0x15 0x15 0x2a 0x33 0x0c 0x0c 0x33 0x00 0x00 0x00 0x30055 0x3000300 0x3000300 0xc0300 0x42080010 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x400320 0x40 0x00 0x00 0x00 0x1000000 0x20003 0x00 0x00 0x00 0x2a 0x15 0x15 0x2a 0x33 0x0c 0x0c 0x33 0x1ee6b16a 0x10000000 0x00 0x30055 0x3000300 0x3000300 0xc0300 0x42080010 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x4000f01 0x20040 0x20055 0x00 0x00 0x00 0x50 0x00 0x1010100 0x600 0x00 0x6400 0x9221902 0x00 0xd1f01 0xd1f0d1f 0xd1f0d1f 0x30003 0x3000300 0x300 0x9221902 0x00 0x00 0x1020000 0x01 0x411 0x411 0x40 0x40 0x411 0x411 0x4410 0x4410 0x4410 0x4410 0x4410 0x411 0x4410 0x411 0x4410 0x411 0x4410 0x00 0x00 0x00 0x64000000 0x00 0x00 0x108 0x00 0x00 0x00 0x00 0x00 0x00 0xe4000000 0x00 0x00 0x1010000 0x00>;
	};

	syscon@ff330000 {
		u-boot,dm-pre-reloc;
		compatible = "rockchip,rk3399-pmusgrf\0syscon";
		reg = <0x00 0xff330000 0x00 0xe3d4>;
	};

	config {
		u-boot,spl-payload-offset = <0x60000>;
	};

	vcc_hub_en-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <0xb7 0x04 0x00>;
		pinctrl-names = "default";
		pinctrl-0 = <0xc0>;
		regulator-name = "vcc_hub_en";
		regulator-always-on;
	};
};